27LV002CB-70 MCNIX [Macronix International], 27LV002CB-70 Datasheet
27LV002CB-70
Related parts for 27LV002CB-70
27LV002CB-70 Summary of contents
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... Data# Polling & Toggle bit for detection of program and erase operation completion. GENERAL DESCRIPTION The MX29LV002C T 2-mega bit Flash memory organized as 256K bytes of 8 bits. MXIC's Flash memo- ries offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV002C T/B is packaged in 32-pin TSOP and 32-pin PLCC ...
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PIN CONFIGURATIONS 32 TSOP (TYPE 1) A11 A13 4 A14 5 A17 6 WE# 7 MX29LV002C/002NC T/B VCC 8 RESET# 9 A16 10 A15 11 A12 ...
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BLOCK DIAGRAM WE# CONTROL OE# INPUT WP# LOGIC RESET# ADDRESS LATCH A0~A17 AND BUFFER Q0-Q7 P/N:PM1204 MX29LV002C/002NC T/B PROGRAM/ERASE HIGH VOLTAGE FLASH ARRAY Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 3 WRITE STATE MACHINE (WSM) ...
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AUTOMATIC PROGRAMMING The MX29LV002C T/B is byte programmable using the Automatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming ...
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VID, as shown in table4. To verify whether or not sector being protected, the sec- tor address must appear on the appropriate highest or- der address bit (see Table 1 and Table 2). ...
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... can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA Address of memory location to be programmed Data to be programmed at location PA Address of the sector to be erased. 3. The system should generate the following address patterns: 555H or 2AAH to Address A11~A0. ...
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COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the TABLE 5. MX29LV002C ...
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... The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors , or the entire device. Table indicates the address space that each sector occupies. A " ...
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... Auto- matic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pat- tern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data " ...
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TABLE 6. EXPANDED SILICON ID CODE Pins A0 A1 Manufacture code VIL VIL Device code VIH VIL for MX29LV002CT Device code VIH VIL for MX29LV002CB Sector Protection X VIH Verification X VIH READING ARRAY DATA The device is automatically set ...
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... When using the Automatic sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array Table 7. Write Operation Status Status Byte Program in Auto Program Algorithm ...
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... The state machine will return to read mode auto- matically after suspend is ready. At this time, state ma- chine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands. The system can determine the status of the program operation using the status bits, just as in the standard program operation ...
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Only erase operations can convert a "0" "1". WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY#. Table 10 and ...
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The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus- pended. When the device is actively erasing (that is, the ...
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... VCC and GND. POWER-UP SEQUENCE The MX29LV002C T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. TEMPORARY SECTOR UNPROTECT This feature allows temporary unprotection of previously protected sector to change data in-system ...
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WE# pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform. To verify programming of the protection circuitry, the pro- gramming equipment ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...
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Table 8. CAPACITANCE SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin Capacitance COUT Output Capacitance Table 9. DC CHARACTERISTICS TA = -40 Symbol PARAMETER ILI Input Leakage Current ILIT A9 Input Leakage Current ILO Output Leakage Current ...
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AC CHARACTERISTICS TA = -40 Table 10. READ OPERATIONS SYMBOL PARAMETER tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE CE# to Output Delay tOE OE# to Output Delay tDF OE# High to Output Float (Note1) tOEH ...
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Figure 1. SWITCHING TEST CIRCUITS DEVICE UNDER TEST Figure 2. SWITCHING TEST WAVEFORMS 3.0V 1. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are ...
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Figure 3. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL VIH RESET# VIL P/N:PM1204 MX29LV002C/002NC T/B tRC ADD Valid tACC tCE tOE tOEH tACC 21 tDF tOH HIGH ...
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AC CHARACTERISTICS TA = -40 Table 11. Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup Time tGHWL Read ...
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AC CHARACTERISTICS TA = -40 Table 12. Alternate CE# Controlled Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup ...
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Figure 4. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE# VIL tOES CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM1204 MX29LV002C/002NC T/B ADD Valid tAH tWP tCWC tCH tDS tDH DIN 24 tWPH ...
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AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. Programming completion can be verified by ...
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Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1204 MX29LV002C/002NC T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES ...
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Figure 7. CE# CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase Address tWC tWH WE# tGHEL OE# CE# tWS Data tRH RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. 2.Figure indicates ...
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AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is verified automatically by internal control circuit. Erasure completion can be veri- fied by Data# Polling and toggle bit checking after ...
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Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1204 MX29LV002C/002NC T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address ...
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AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector indicated by A12 to A17 are erased. External erase verify is not required because data are verified automatically by internal control circuit. Erasure comple- tion can be verified by Data# Polling and toggle bit ...
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Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1204 MX29LV002C/002NC T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector ...
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Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART Note: If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times, then the 10ms time delay must be put into consideration. P/N:PM1204 MX29LV002C/002NC T/B START ...
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Figure 13. IN-SYSTEM SECTOR PROTECT/UNPROTECT TIMING WAVEFORM (RESET# Control) VID VIH RESET# SA, A6 A1, A0 Sector Protect or Sector Unprotect Data 60h 1us CE# WE# OE# Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0. ...
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Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=25? Yes Device failed P/N:PM1204 MX29LV002C/002NC T/B START PLSCNT=1 RESET#=VID Wait 1us No First Write Cycle=60H Yes Set up sector address Write 60H to sector address with A6=0, A1=1, ...
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Figure 15. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control 12V 3V A9 tVLHT 12V 3V OE# tVLHT WE# CE# Data A18-A12 P/N:PM1204 MX29LV002C/002NC T/B tWPP 1 tOESP Sector Address 35 Verify tVLHT 01H F0H tOE REV. 1.0, JUN. ...
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Figure 16. SECTOR PROTECTION ALGORITHM (A9, OE# Control) No PLSCNT=32? Yes Device Failed P/N:PM1204 MX29LV002C/002NC T/B START Set Up Sector Addr PLSCNT=1 OE#=VID, A9=VID, CE#=VIL A6=VIL Activate WE# Pulse Time Out 150us Set WE#=VIH, CE#=OE#=VIL A9 should remain VID Read ...
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Figure 17. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=1000? Yes Device failed P/N:PM1204 MX29LV002C/002NC T/B START PLSCNT=1 RESET#=VID Wait 1us No First Write Cycle=60H ? Yes No All sector protected? Yes Set up first sector address Chip ...
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Figure 18. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control) A1 12V 3V A9 tVLHT A6 12V 3V OE# tVLHT WE# CE# Data A18-A12 Notes: tWPP1 (Write pulse width for sector protect)=100ns min, 10us(typ.). tWPP2 (Write pulse width for sector ...
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Figure 19. CHIP UNPROTECTION ALGORITHM (A9, OE# Control) Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1204 MX29LV002C/002NC T/B START Protect All Sectors PLSCNT=1 Set OE#=A9=VID CE#=VIL, A6=1 Activate WE# ...
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WRITE OPERATION STATUS Figure 20. DATA# POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change P/N:PM1204 MX29LV002C/002NC T/B Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? ...
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Figure 21. TOGGLE BIT ALGORITHM NO Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM1204 MX29LV002C/002NC T/B Start Read Q7-Q0 Read Q7-Q0 ...
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Figure 22. DATA# POLLING TIMINGS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# Q7 Q0-Q6 tBUSY RY/BY# NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, ...
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Figure 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# High Z Q6/Q2 tBUSY RY/BY# NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after ...
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Table 13. AC CHARACTERISTICS (for 32-pin TSOP package type) Parameter Std Description tREADY1 RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP ...
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Table 14. TEMPORARY SECTOR UNPROTECT Parameter Std. Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect Note: Not 100% tested Figure 25. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM 12V RESET Vcc ...
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Figure 27. TEMPORARY SECTOR UNPROTECT ALGORITHM Temporary Sector Unprotect Completed(Note 2) Note : P/N:PM1204 MX29LV002C/002NC T/B Start RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V ...
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Figure 28. ID CODE READ TIMING WAVEFORM VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A18 VIL CE# VIH VIL VIH WE# VIL VIH OE# VIL VIH DATA Q0-Q7 VIL ...
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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...
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Table 15. ERASE AND PROGRAMMING PERFORMANCE(1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured 3V. 3.Maximum values ...
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QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE ( for MX29LV002CT/ CB) MX29LV002CT/CB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating param- eters and ...
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TABLE 18-3. CFI Mode: Device Geometry Data Values (All values in these tables are in hexadecimal) Description N Device size (2 bytes) Flash device interface code (refer to the CFI publication 100) Maximum number of bytes in multi-byte write (not ...
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ORDERING INFORMATION PART NO. Access Time (ns) MX29LV002CTTC-70 70 MX29LV002CBTC-70 70 MX29LV002CTTC-90 90 MX29LV002CBTC-90 90 MX29LV002CTTI-70 70 MX29LV002CBTI-70 70 MX29LV002CTTI-90 90 MX29LV002CBTI-90 90 MX29LV002CTQC-70 70 MX29LV002CBQC-70 70 MX29LV002CTQC-90 70 MX29LV002CBQC-90 70 MX29LV002CTQI-70 70 MX29LV002CBQI-70 70 MX29LV002CTQI-90 70 MX29LV002CBQI-90 70 MX29LV002CTTC-70G ...
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PART NO. Access Time (ns) MX29LV002NCTTC-70 70 MX29LV002NCBTC-70 70 MX29LV002NCTTC-90 90 MX29LV002NCBTC-90 90 MX29LV002NCTTI-70 70 MX29LV002NCBTI-70 70 MX29LV002NCTTI-90 90 MX29LV002NCBTI-90 90 MX29LV002NCTQC-70 70 MX29LV002NCBQC-70 70 MX29LV002NCTQC-90 70 MX29LV002NCBQC-90 70 MX29LV002NCTQI-70 70 MX29LV002NCBQI-70 70 MX29LV002NCTQI-90 70 MX29LV002NCBQI-90 70 MX29LV002NCTTC-70G 70 MX29LV002NCTTC-90G ...
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PART NAME DESCRIPTION 002/002N C P/N:PM1204 MX29LV002C/002NC T OPTION: G: Lead-free package R: Restricted VCC (3.0V~3.6V) Q: Restricted VCC (3.0V~3.6V) with Lead-free package SPEED: 70: 70ns 90: 90ns TEMPERATURE RANGE: C: Commercial ...
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PACKAGE INFORMATION P/N:PM1204 MX29LV002C/002NC T/B 55 REV. 1.0, JUN. 30, 2005 ...
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P/N:PM1204 MX29LV002C/002NC T/B 56 REV. 1.0, JUN. 30, 2005 ...
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REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 2. Added "Recommended Operating Conditions" P/N:PM1204 MX29LV002C/002NC T/B 57 Page Date P1 JUN/30/2005 P48 REV. 1.0, JUN. 30, 2005 ...
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MX29LV002C/002NC T/B http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...