LM2651MTCX-1.8 NSC [National Semiconductor], LM2651MTCX-1.8 Datasheet - Page 9

• Manufacturer Part Number: LM2651MTCX-1.8
• Description: 1.5A High Efficiency Synchronous Switching Regulator
• Manufacturer: NSC [National Semiconductor]

Design Procedure
Select resistors between 10k and 100k . (1% or higher ac-
curacy metal film resistors for R
COMPENSATION COMPONENTS
In the control to output transfer function, the first pole F
be estimated as 1/(2 R
output capacitor is 1/(2 ESRC
quency pole F
where D = V
and V
The total loop gain G is approximately 500/I
is in amperes.
A Gm amplifier is used inside the LM2651. The output resis-
tor R
gether with R
In some applications, the ESR zero F
by F
ESR zero, F
The rule of thumb is to have more than 45˚ phase margin at
the crossover frequency (G = 1).
If C
good choices for most applications. If the ESR zero is too
low to be cancelled by F
If the transient response to a step load is important, choose
R
EXTERNAL SCHOTTKY DIODE
A Schottky diode D
body diode of the low-side MOSFET from conducting during
the deadtime in PWM operation and hysteretic mode when
both MOSFETs are off. If the body diode turns on, there is
extra power dissipation in the body diode because of the
reverse-recovery current and higher forward voltage; the
high-side MOSFET also has more switching loss since the
negative diode reverse-recovery current appears as the
C
OUT
to be higher than 10k .
p2
o
IN
. Then, C
of the Gm amplifier is about 80k . C
is higher than 68µF, C
F
and V
pc1
p2
OUT
= 1/(2 C
o
p2
OUT
give a lag compensation to roll off the gain:
= 1/(2 C
c2
/V
in the range of 45kHz to 150kHz:
is needed to introduce F
IN
1
in volts).
F
, n = 1+0.348L/(V
is recommended to prevent the intrinsic
p2
c1
OUT
(R
c2
= F
p2
o
R
, add C
+R
C
o
s
\R
OUT
/( n(1−D))
c1
c
OUT
)), F
c
(Continued)
).
= 2.2nF, and R
1
); The ESR zero F
and R
); Also, there is a high fre-
c2
zc1
.
z1
IN
= 1/2 C
can not be cancelled
2
−V
.)
Schematic for the Typical Board Layout
OUT
pc2
OUT
c1
c
) (L is in µHs
to cancel the
c1
= 15K are
where I
and R
R
c
.
z1
p1
of the
C
can
OUT
to-
9
high-side MOSFET turn-on current in addition to the load
current. These losses degrade the efficiency by 1-2%. The
improved efficiency and noise immunity with the Schottky di-
ode become more obvious with increasing input voltage and
load current.
The breakdown voltage rating of D
higher than the maximum input voltage. Since D
for a short period of time, the average current rating for D
only requires being higher than 30% of the maximum output
current. It is important to place D
source of the low-side MOSFET, extra parasitic inductance
in the parallel loop will slow the turn-on of D
current through the body diode of the low-side MOSFET.
When an undervoltage situation occurs, the output voltage
can be pulled below ground as the inductor current is re-
versed through the synchronous FET. For applications which
need to be protected from a negative voltage, a clamping di-
ode D2 is recommended. When used, D2 should be con-
nected cathode to V
for a minimum of 2A is recommended.
PCB Layout Considerations
Layout is critical to reduce noises and ensure specified per-
formance. The important guidelines are listed as follows:
1. Minimize the parasitic inductance in the loop of input ca-
2. Minimize the trace from the center of the output resistor
3. If the Schottky diode D
pacitors and the internal MOSFETs by connecting the in-
put capacitors to V
traces. This is important because the rapidly switching
current, together with wiring inductance can generate
large voltage spikes that may result in noise problems.
divider to the FB pin and keep it away from noise
sources to avoid noise pick up. For applications requir-
ing tight regulation at the output, a dedicated sense
trace (separated from the power trace) is recommended
to connect the top of the resistor divider to the output.
connecting D
1
to SW and PGND pins.
OUT
IN
and anode to ground. A diode rated
and PGND pins with short and wide
1
DS100925-23
is used, minimize the traces
1
very close to the drain and
1
is preferred to be 25%
1
and direct the
1
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is only on
1