A4402_1 ALLEGRO [Allegro MicroSystems], A4402_1 Datasheet - Page 15

• Manufacturer Part Number: A4402_1
• Description: Constant On-Time Buck Converter with Integrated Linear Regulator
• Manufacturer: ALLEGRO [Allegro MicroSystems]

A4402
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Copyright ©2008-2009, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
16X
0.10
0.25
+0.05
–0.06
C
16
1
A
2
5.00 ±0.10
B
3.00
0.65
For the latest version of this document, visit our website:
3.00
0.15 MAX
Package LP, 16-Pin TSSOP
SEATING
PLANE
1.20 MAX
4.40 ±0.10
www.allegromicro.com
C
6.40 ±0.20
Constant On-Time Buck Converter
A Terminal #1 mark area
B
C
with Integrated Linear Regulator
All dimensions nominal, not for tooling use
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Exposed thermal pad (bottom surface)
GAUGE PLANE
0.25
4° ±4
0.60 ±0.15
SEATING PLANE
0.15
(1.00)
+0.05
–0.06
1.70
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
C
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
16
1
PCB Layout Reference View
2
0.45
3.00
3.00
0.65
6.10
15