LM5067MM-1 NSC [National Semiconductor], LM5067MM-1 Datasheet - Page 11

• Manufacturer Part Number: LM5067MM-1
• Description: Negative Hot Swap / Inrush Current Controller with Power Limiting
• Manufacturer: NSC [National Semiconductor]

Functional Description
The LM5067 is designed to control the in-rush current to the
load upon insertion of a circuit card into a live backplane or
other “hot” power source, thereby limiting the voltage sag on
the backplane’s supply voltage, and the dV/dt of the voltage
applied to the load. Effects on other circuits in the system are
minimized, preventing possible unintended resets. During the
system power up, the maximum power dissipation in the se-
ries pass device is limited to a safe value within the device’s
Safe Operating Area (SOA). After the system power up is
complete, the LM5067 monitors the load for excessive cur-
rents due to a fault or short circuit at the load. Limiting the load
current and/or the power in the external MOSFET for an ex-
The LM5067 can be used in a variety of applications, other
than plug-in boards, to monitor for excessive load current,
provide transient protection, and ensuring the voltage to the
load is within preferred limits. The circuit breaker function
protects the system from a sudden short circuit at the load.
Use of the UVLO/EN pin allows the LM5067 to be used as a
solid state relay. The PGD output provides a status indication
of the voltage at the load relative to the input system voltage.
Power Up Sequence
The system voltage range of the LM5067 is -9V to -80V, with
a transient capability to -100V. Referring to the Block Diagram
and Figures 1 and 3, as the system voltage (V
increases from zero, the external N-channel MOSFET (Q1) is
held off by an internal 110 mA pull-down current at the GATE
pin. The strong pull-down current at the GATE pin prevents
an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller)
capacitance is charged. When the operating voltage of the
LM5067 (VCC – VEE) reaches the POR
insertion timer starts. During the insertion time, the capacitor
at the TIMER pin (C
and Q1 is held off by a 2.2 mA pull-down current at the GATE
pin regardless of the system voltage. The insertion time delay
allows ringing and transients at V
be enabled. The insertion time ends when the TIMER pin
voltage reaches 4.0V above VEE, and C
charged by an internal 1.5 mA pull-down current. After the
insertion time, the LM5067 control circuitry is enabled when
T
) is charged by a 6 µA current source,
SYS
to settle before Q1 can
IT
T
threshold (7.7V) the
is then quickly dis-
FIGURE 2. LM5067 Application
SYS
) initially
11
tended period of time results in the shutdown of the series
pass MOSFET. After a fault event, the LM5067-1 latches off
until the circuit is re-enabled by external control, while the
LM5067-2 automatically restarts with defined timing. The cir-
cuit breaker function quickly switches off the series pass
device upon detection of a severe over-current condition
caused by, e.g. a short circuit at the load. The Power Good
(PGD) output pin indicates when the output voltage is close
to the normal operating value. Programmable under-voltage
lock-out (UVLO) and over-voltage lock-out (OVLO) circuits
shut down the LM5067 when the system input voltage is out-
side the desired operating range. The typical configuration of
a circuit card with LM5067 hot swap protection is shown in
Figure 2.
the operating voltage reaches the POR
As V
is limited at
of the system voltage is dropped across the input resistor
R
The GATE pin switches on Q1 when V
threshold (UVLO pin >2.5V above VEE). If V
UVLO threshold at the end of the insertion time, Q1 is
switched on at that time. The GATE pin sources 52 µA to
charge Q1’s gate capacitance. The maximum gate-to-source
voltage of Q1 is limited by the LM5067’s operating voltage
(V
at the OUT pin increases in magnitude with respect to
Ground, the LM5067 monitors Q1’s drain current and power
dissipation. In-rush current limiting and/or power limiting cir-
cuits actively control the current delivered to the load. During
the in-rush limiting interval (t2 in Figure 3) an internal current
source charges C
reduces from the limiting value to a value determined by the
load the in-rush limiting interval is complete and C
charged. The PGD pin switches high when the voltage at the
OUT pin reaches to within 1.25V of the voltage at the SENSE
pin.
If the TIMER pin voltage reaches 4.0V before in-rush current
limiting or power limiting ceases (during t2), a fault is declared
and Q1 is turned off. See the Fault Timer & Restart section
for a complete description of the fault mode.
IN
Z
.
) to approximately 13V. During power up, as the voltage
SYS
continues to increase, the LM5067 operating voltage
≊
13V by an internal zener diode. The remainder
T
at the TIMER pin. When the load current
30030929
SYS
EN
exceeds the UVLO
threshold (8.4V).
SYS
exceeds the
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T
is dis-