STM8S103XX STMICROELECTRONICS [STMicroelectronics], STM8S103XX Datasheet - Page 31

• Manufacturer Part Number: STM8S103XX
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STM8S103xx, STM8S105xx
6
Table 7.
Addr.
480Ch
480Dh
4800h
4801h
4802h
4803h
4804h
4805h
4806h
4807h
4808h
4809h
480Ah
480Bh
480Eh
487Eh
487Fh
Read-out
protection
(ROP)
code(UBC)
Alternate
function
remapping
(AFR)
Watchdog
option
Clock option
HSE clock
startup
Reserved
Flash wait
states
Bootloader
User boot
Option
name
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the address shown in
Table 7: Option bytes
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be toggled in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Option bytes
Option
NOPTBL
NOPT1
NOPT2
NOPT3
NOPT4
NOPT5
NOPT6
NOPT7
OPTBL
byte
OPT0
OPT1
OPT2
OPT3
OPT4
OPT5
OPT6
OPT7
no.
NAFR7
AFR7
7
below.
NAFR6
AFR6
6
Reserved
Reserved
Reserved
Reserved
NAFR5
AFR5
5
NAFR4
Reserved
Reserved
AFR4
4
Option bits
NHSECNT[7:0]
HSECNT[7:0]
NUBC[7:0]
Reserved
Reserved
ROP[7:0]
UBC[7:0]
NBL[7:0]
BL[7:0]
NAFR3
NEXT
AFR3
NLSI
_EN
_EN
EXT
CLK
CLK
LSI
3
NCKAWUS
NIWDG_
CKAWU
NAFR2
IWDG
AFR2
_HW
SEL
HW
EL
2
NWWDG
WWDG
NAFR1
AFR1
_HW
_HW
PRS
NPR
SC1
C1
1
Nwait state
Wait state
NAFR0
WWDG
NWWG
_HALT
_HALT
AFR0
PRS
NPR
SC0
C0
0
Option bytes
Factory
default
setting
00h
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
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