AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 254

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

21.8.4.2
21.8.5
21.8.6
21.9
254
Amplifier
AT90PWM216/316
Digital Input Disable Register 0 – DIDR0
Digital Input Disable Register 1– DIDR1
ADLAR = 1
• Bit 7:0 – ADC7D..ADC0D: ACMP2:1 and ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
• Bit 5:0 – ACMP0D, AMP0+D, AMP0-D, ADC10D..ADC8D: ACMP0, AMP1:0 and ADC10:8
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
The AT90PWM216/316 features two differential amplified channels with programmable 5, 10,
20, and 40 gain stage. Despite the result is given by the 10 bit ADC, the amplifier has been sized
to give a 8bits resolution.
Because the amplifier is a switching capacitor amplifier, it needs to be clocked by a synchroniza-
tion signal called in this document the amplifier synchronization clock. The maximum frequency
of this clock is 250KHz.
To ensure an accurate result, the amplifier input needs to have a quite stable input value at the
sampling point during at least 4 Amplifier synchronization clock periods.
Amplified conversions can be synchronized to PSC events (See
Description in One/Two/Four Ramp Modes” on page 163
tion in Centered Mode” on page
clock frequency. In case the synchronization is done by the ADC clock divided by 8, this syn-
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Digital Input Disable
ADC7D
ADC9
ADC1
R/W
R
R
7
0
0
7
0
7
0
-
-
ADC6D
ADC8
ADC0
R/W
6
0
6
0
R
R
6
0
0
-
-
ACMP0D
ADC5D
ADC7
163) or to the internal clock CK
R/W
R/W
R
R
5
0
5
0
5
0
0
-
AMP0PD
ADC4D
ADC6
R/W
R/W
R
R
4
0
4
0
4
0
0
-
AMP0ND
ACMPM
ADC3D
ADC5
R/W
R/W
R
R
3
0
0
3
0
3
0
-
and
ACMP2D
ADC10D
ACMP1D
ADC2D
ADC4
R/W
R/W
“Synchronization Source Descrip-
R
R
2
0
2
0
2
0
0
-
ADC
AMP1PD
ADC1D
ADC9D
“Synchronization Source
ADC3
R/W
R/W
equal to eighth the ADC
R
R
1
0
0
1
0
1
0
-
AMP1ND
ADC0D
ADC8D
ADC2
R/W
R/W
R
R
0
0
0
0
0
0
0
-
7710D–AVR–08/09
ADCH
ADCL
DIDR0
DIDR1