AT90S2313_02 ATMEL [ATMEL Corporation], AT90S2313_02 Datasheet
AT90S2313_02
Related parts for AT90S2313_02
AT90S2313_02 Summary of contents
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Features ® • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 118 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – MIPS Throughput ...
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Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power ...
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Pin Descriptions VCC GND Port B (PB7..PB0) Port D (PD6..PD0) RESET XTAL1 XTAL2 0839I–AVR–06/02 selectable power-saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The Power-down mode saves ...
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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier that can be configured for use as an On-chip Oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. ...
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Architectural Overview 0839I–AVR–06/02 The fast-access Register File concept contains 32 x 8-bit general purpose working reg- isters with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. ...
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The I/O memory space contains 64 addresses for CPU peripheral functions such as control registers, Timer/Counters, A/D converters and other I/O functions. The I/O mem- ory can be accessed directly or as the Data Space locations following those of the ...
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General Purpose Register File X-register, Y-register, and Z- register 0839I–AVR–06/02 Figure 6 shows the structure of the 32 general purpose registers in the CPU. Figure 6. AVR CPU General Purpose Working Registers 7 General Purpose Working Registers All the register ...
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In the different addressing modes these address registers have functions as fixed dis- placement, automatic increment and decrement (see the descriptions for the different instructions). ALU – Arithmetic Logic The high-performance AVR ALU operates in direct connection with all the ...
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SRAM Data Memory 0839I–AVR–06/02 Figure 8 shows how the AT90S2313 data memory is organized. Figure 8. SRAM Organization Register File … R29 R30 R31 I/O Registers $00 $01 $02 … $3D $3E $3F The 224 data memory ...
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Program and Data The AT90S2313 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the Program memory (Flash) and Data memory. This section Addressing Modes describes the different addressing modes supported by the AVR architecture. In the ...
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Data Direct Data Indirect with Displacement Data Indirect 0839I–AVR–06/02 Operand address is contained in 6 bits of the instruction word the destination or source register address. Figure 12. Direct Data Addressing A 16-bit data address is contained in ...
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Data Indirect with Pre- Figure 15. Data Indirect Addressing with Pre-decrement decrement The X-, Y-, or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or Z-register. Data Indirect with Post- Figure 16. ...
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Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL 0839I–AVR–06/02 Figure 18. Indirect Program Memory Addressing Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Figure ...
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Memory Access and This section describes the general access timing concepts for instruction execution and internal memory access. Instruction Execution Timing The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the ...
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I/O Memory 0839I–AVR–06/02 Figure 22. On-chip Data SRAM Access Cycles T1 System Clock Ø Address Prev. Address Data WR Data RD The I/O space definition of the AT90S2313 is shown in Table 1. (1) Table 1. AT90S2313 I/O Space Address ...
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Table 1. AT90S2313 I/O Space Note: All AT90S2313 I/O and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general pur- pose working registers and the ...
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Stack Pointer – SP 0839I–AVR–06/02 • Bit 5 – H: Half-carry Flag The Half-carry Flag H indicates a Half-carry in some arithmetic operations. See the Instruction Set description for detailed information. • Bit 4 – S: Sign Bit ...
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Reset and Interrupt The AT90S2313 provides 10 different interrupt sources. These interrupts and the sepa- rate Reset Vector each have a separate Program Vector in the program memory space. Handling All the interrupts are assigned individual enable bits that must ...
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Reset Sources 0839I–AVR–06/02 The AT90S2313 has three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. The MCU is reset when a low ...
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Table 4. Number of Watchdog Oscillator Cycles Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. As shown in Figure 23, an internal timer is clocked from the Watchdog Timer. This timer prevents the ...
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External Reset Watchdog Reset Interrupt Handling 0839I–AVR–06/02 An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are ...
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Some of the Interrupt Flags can also be cleared by writing a logical “1” to the flag bit position( cleared interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the Interrupt Flag ...
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General Interrupt FLAG Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK 0839I–AVR–06/02 Bit $3A ($5A) INTF1 INTF0 – Read/Write R/W R/W R Initial value • Bit 7 – INTF1: External Interrupt Flag1 When ...
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Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector ...
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External Interrupts Interrupt Response Time MCU Control Register – MCUCR 0839I–AVR–06/02 • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and always reads as zero. • Bit 1 – TOV0: Timer/Counter0 Overflow Flag ...
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Bit 4 – SM: Sleep Mode This bit selects between the two available sleep modes. When SM is cleared (zero), Idle mode is selected as sleep mode. When SM is set (one), Power-down mode is selected as sleep mode. ...
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Sleep Modes Idle Mode Power-down Mode Timer/Counters Timer/Counter Prescaler 0839I–AVR–06/02 To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc- tion must be executed enabled interrupt occurs while the MCU ...
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The four different prescaled selections are: CK/8, CK/64, CK/256, and CK/1024, where CK is the Oscillator clock. For the two Timer/Counters, added selections such as CK, external clock source and stop can be selected as clock sources. 8-bit Timer/Counter0 Figure ...
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Timer/Counter0 Control Register – TCCR0 Timer/Counter0 – TCNT0 0839I–AVR–06/02 Bit $33 ($53) – – – Read/Write Initial value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in ...
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Timer/Counter1 Figure 30 shows the block diagram for Timer/Counter1. Figure 30. Timer/Counter1 Block Diagram The 16-bit Timer/Counter1 can select clock source from CK, prescaled exter- nal pin. In addition, it can be stopped as described in ...
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Timer/Counter1 Control Register A – TCCR1A 0839I–AVR–06/02 Timer/Counter1 can also be used as an 8-, 9-, or 10-bit Pulse Width Modulator. In this mode the counter and the OCR1 Register serve as a glitch-free standalone PWM with centered pulses. Refer ...
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Bits 1, 0 – PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 9. This mode is described on page 35. Table 9. PWM Mode Select Timer/Counter1 Control Register B ...
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Timer/Counter1 – TCNT1H and TCNT1L 0839I–AVR–06/02 • Bits 2,1,0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0 The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 10. Clock 1 Prescale Select ...
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The Timer/Counter1 is realized up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it ...
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Timer/Counter1 in PWM Mode 0839I–AVR–06/02 The TEMP Register is also used when accessing TCNT1 and OCR1A. If the main pro- gram and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program ...
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During the time between the write and the latch operations, a read from OCR1A will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A. When the OCR1 contains ...
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Watchdog Timer Watchdog Timer Control Register – WDTCR 0839I–AVR–06/02 The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz. This is the typical value 5V. See characterization data for typical values at ...
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In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must 2. Within the next four clock cycles, write a logical “0” to WDE. This disables the • Bits 2..0 – WDP2, WDP1, WDP0: ...
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EEPROM Read/Write Access EEPROM Address Register – EEAR EEPROM Data Register – EEDR 0839I–AVR–06/02 The EEPROM Access Registers are accessible in the I/O space. The write access time is in the range of 2 ms, depending on the ...
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EEPROM Control Register – EECR • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and will always read as zero. • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether ...
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Prevent EEPROM Corruption 0839I–AVR–06/02 During periods of low V , the EEPROM data can be corrupted because the supply volt- CC age is too low for the CPU and the EEPROM to operate properly. These issues are the same as ...
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UART The AT90S2313 features a full duplex (separate Receive and Transmit Registers) Uni- versal Asynchronous Receiver and Transmitter (UART). The main features are: • • • • • • • • Data Transmission A block schematic of the UART transmitter ...
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Data Reception 0839I–AVR–06/02 tus Register (USR) is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDR to the 10(11)-bit Shift Register, bit ...
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If, however, a valid start bit is detected, sampling of the data bits following the start ...
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UART Control The UART I/O Data Register – UDR UART Status Register – USR 0839I–AVR–06/02 Bit $0C ($2C) MSB Read/Write R/W R/W R/W Initial value The UDR Register is actually two physically separate registers ...
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Bit 4 – FE: Framing Error This bit is set if a Framing Error condition is detected (i.e., when the stop bit of an incom- ing character is zero). The FE bit is cleared when the stop bit of ...
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Baud Rate Generator 0839I–AVR–06/02 • Bit 1 – RXB8: Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character. • Bit 0 – TXB8: Transmit Data Bit 8 When CHR9 is ...
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UART Baud Rate Register – UBRR The UBRR Register is an 8-bit read/write register that specifies the UART Baud Rate according to the formula on the previous page. Analog Comparator The Analog Comparator compares the input values on the positive ...
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Bit 5 – ACO: Analog Comparator Output ACO is directly connected to the comparator output. • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode ...
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I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the ...
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Port B as General Digital I/O Alternate Functions of Port B 0839I–AVR–06/02 The Port B Input Pins address (PINB) is not a register; this address enables access to the physical value on each Port B pin. When reading PORTB, the ...
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Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 38. Port B Schematic Diagram (Pins PB0 and PB1) AT90S2313 52 0839I–AVR–06/02 ...
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Figure 39. Port B Schematic Diagram (Pin PB3) MOS PULL- UP PB3 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB Figure 40. Port B Schematic Diagram (Pins PB2 and PB4) ...
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Figure 41. Port B Schematic Diagram (Pin PB5) Figure 42. Port B Schematic Diagram (Pin PB6) AT90S2313 54 0839I–AVR–06/02 ...
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Port D 0839I–AVR–06/02 Figure 43. Port B Schematic Diagram (Pin PB7) Three I/O memory address locations are allocated for the Port D: one each for the Data Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port ...
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Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND The Port D Input Pins address (PIND) is not a register; this address enables access to the physical value on ...
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Port D Schematics 0839I–AVR–06/02 • INT1 – Port D, Bit 3 INT1, External Interrupt Source 1. The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable ...
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Figure 45. Port D Schematic Diagram (Pin PD1) Figure 46. Port D Schematic Diagram (Pins PD2 and PD3) AT90S2313 58 MOS PULL- UP PD1 WRITE PORTD WP: WD: WRITE DDRD RL: READ PORTD LATCH READ PORTD PIN RP: RD: READ ...
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Figure 47. Port D Schematic Diagram (Pins PD4 and PD5) MOS PULL- UP PDn WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD Figure 48. ...
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Memory Programming Program and Data The AT90S2313 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 21. The Lock bits Memory Lock Bits can only ...
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Parallel Programming Signal Names 0839I–AVR–06/02 within the self-timed write instruction in the Serial Programming mode. During program- ming, the supply voltage must be in accordance with Table 22. Table 22. Supply Voltage during Programming Part Serial Programming AT90S2313 2.7 - ...
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Table 23. Pin Name Mapping Table 24. XA1 and XA0 Coding Table 25. Command Byte Bit Coding Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply supply voltage according to Table 22, between V ...
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Programming the Flash 0839I–AVR–06/02 5. Give WR a wide negative pulse to execute Chip Erase. See Table 26 t WLWH_CE for value. Chip Erase does not generate any activity on the RDY/BSY t WLWH_CE pin. A: Load Command “Write Flash” ...
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The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered: • • • These considerations also apply to EEPROM programming and Flash, EEPROM and signature byte reading. Figure 50. Programming ...
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Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits 0839I–AVR–06/02 The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” for details on command and address loading): ...
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Reading the Fuse and Lock The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming Bits the Flash” on page 63 for details on command loading Load Command “0000 0100”. 2. Set OE ...
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Parallel Programming Characteristics 0839I–AVR–06/02 Figure 52. Parallel Programming Timing t XTAL1 XHXL t DVXH Data & Contol (DATA, XA0/1, BS) WR RDY/BSY OE DATA Table 26. Parallel Programming Characteristics, T Symbol Parameter V Programming Enable Voltage PP I Programming Enable ...
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Serial Downloading Both the program and data memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See Figure 53. After RESET ...
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Data Polling EEPROM 0839I–AVR–06/02 ing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive ...
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Data Polling Flash When a byte is being programmed into the Flash, reading the address location being programmed will give the value $7F. At the time the device is ready for a new byte, the programmed value will read correctly. ...
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Serial Programming Characteristics 0839I–AVR–06/02 Figure 55. Serial Programming Timing MOSI t OVSH SCK MISO Table 29. Serial Programming Characteristics, T (unless otherwise noted) Symbol Parameter 1/t Oscillator Frequency (V CLCL CC t Oscillator Period (V = 2.7 - 6.0V) CLCL ...
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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. - +125 C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin Except RESET with Respect to Ground ...............................-1. Voltage on RESET with Respect to Ground ....-1.0V to ...
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External Clock Drive Waveforms 0839I–AVR–06/02 Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low. 2. “Min” means the lowest value where the pin is guaranteed to be read as high. 3. Although ...
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Typical The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins Characteristics configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- ...
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Figure 58. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 3.5 Figure 59. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY ...
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Figure 60. Idle Supply Current vs. V Figure 61. Power-down Supply Current vs. V AT90S2313 76 CC IDLE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz 3.5 3 2.5 2 1 2.5 3 3.5 POWER DOWN ...
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Figure 62. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 160 140 120 100 2.5 3 3.5 Figure 63. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT ...
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Note: Figure 64. Analog Comparator Offset Voltage vs. Common Mode Voltage Figure 65. Analog Comparator Offset Voltage vs. Common Mode Voltage AT90S2313 78 Analog Comparator offset voltage is measured as absolute offset. ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE ...
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Figure 66. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 Figure 67. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 ...
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Note: Figure 68. Pull-up Resistor Current vs. Input Voltage Figure 69. Pull-up Resistor Current vs. Input Voltage AT90S2313 80 Sink and source capabilities of I/O ports are measured on one pin at a time. PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...
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Figure 70. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 1 Figure 71. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE ...
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Figure 72. I/O Pin Sink Current vs. Output Voltage Figure 73. I/O Pin Source Current vs. Output Voltage AT90S2313 82 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 V ...
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Figure 74. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 75. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 ...
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Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) Reserved $3D ($5D) SPL SP7 $3C ($5C) Reserved $3B ($5B) GIMSK INT1 $3A ($5A) GIFR INTF1 $39 ($59) TIMSK TOIE1 $38 ($58) TIFR TOV1 $37 ($57) Reserved $36 ...
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Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...
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Instruction Set Summary (Continued) Mnemonic Operands Description DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move between Registers LDI Rd, K Load Immediate LD Rd, X Load Indirect LD Rd, X+ Load Indirect and Post-Inc. LD Rd, -X Load Indirect and Pre-Dec. ...
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Ordering Information Speed (MHz) Power Supply 4 2.7 - 6.0V 10 4.0 - 6.0V 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 0839I–AVR–06/02 Ordering Code Package AT90S2313-4PC 20P3 AT90S2313-4SC ...
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Packaging Information 20P3 A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 ...
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Plastic Gull Wing Small Outline (SOIC), 0.300" body. Dimensions in Millineters and (Inches)* JEDEC STANDARD MS-013 REV. A 04/11/2001 0839I–AVR–06/02 0.51(0.020) 0.33(0.013) PIN 1 ID PIN 1 1.27 (0.050) BSC 13.00 (0.5118) 12.60 (0.4961) 0.30(0.0118) 0.10 (0.0040) ...
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Table of Contents 0839I–AVR–06/02 Features................................................................................................. 1 Pin Configuration.................................................................................. 1 Description ............................................................................................ 2 Pin Descriptions.................................................................................................... 3 Crystal Oscillator................................................................................................... 4 Architectural Overview......................................................................... 5 General Purpose Register File ............................................................................. 7 ALU – Arithmetic Logic Unit.................................................................................. 8 In-System Programmable Flash Program Memory .............................................. 8 ...
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Electrical Characteristics................................................................... 72 Typical Characteristics ...................................................................... 74 Register Summary .............................................................................. 84 Instruction Set Summary ................................................................... 85 Ordering Information.......................................................................... 87 Packaging Information ....................................................................... 88 Table of Contents .................................................................................. i AT90S2313 ii Parallel Programming ......................................................................................... 61 Parallel Programming Characteristics ................................................................ 67 Serial ...
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Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem ...