ATMEGA644V_10 ATMEL [ATMEL Corporation], ATMEGA644V_10 Datasheet

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ATMEGA644V_10

Manufacturer Part Number
ATMEGA644V_10
Description
8-bit Microcontroller with 64K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

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Features
Notes:
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Speed Grades
Power Consumption at 1 MHz, 3V, 25⋅C
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– 64 Kbytes of In-System Self-programmable Flash program memory
– 2 Kbytes EEPROM
– 4 Kbytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– One Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
– ATmega644V: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 10 MHz @ 2.7V - 5.5V
– ATmega644: 0 - 10 MHz @ 2.7V - 5.5V, 0 - 20 MHz @ 4.5V - 5.5V
– Active: 240 µA @ 1.8V, 1 MHz
– Power-down Mode: 0.1 µA @ 1.8V
Mode
and Extended Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Differential mode with selectable gain at 1x, 10x or 200x
1. Worst case temperature. Guaranteed after last write cycle.
2. Failure rate less than 1 ppm.
3. Characterized through accelerated tests.
®
AVR
®
8-bit Microcontroller
(1)(3)
(2)(3)
8-bit
Microcontroller
with 64K Bytes
In-System
Programmable
Flash
ATmega644/V
Preliminary
Summary
2593NS–AVR–07/10

Related parts for ATMEGA644V_10

ATMEGA644V_10 Summary of contents

Page 1

Features • High-performance, Low-power Atmel • Advanced RISC Architecture – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – MIPS Throughput at 20 MHz • ...

Page 2

Pin Configurations Figure 1-1. Note: 2593NS–AVR–07/10 Pinout ATmega644 (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/INT0) PD2 (PCINT27/INT1) PD3 (PCINT28/OC1B) PD4 ...

Page 3

Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. Overview The ATmega644 ...

Page 4

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in ...

Page 5

As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not ...

Page 6

AVCC AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. It should be exter- nally connected through a low-pass filter. CC 2.2.11 AREF This is the analog reference pin for the ...

Page 7

... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 2593NS–AVR–07/10 ATmega644 7 ...

Page 8

Register Summary Address Name Bit 7 (0xFF) Reserved - (0xFE) Reserved - (0xFD) Reserved - (0xFC) Reserved - (0xFB) Reserved - (0xFA) Reserved - (0xF9) Reserved - (0xF8) Reserved - (0xF7) Reserved - (0xF6) Reserved - (0xF5) Reserved - ...

Page 9

Address Name Bit 7 (0xBF) Reserved - (0xBE) Reserved - (0xBD) TWAMR TWAM6 (0xBC) TWCR TWINT (0xBB) TWDR (0xBA) TWAR TWA6 (0xB9) TWSR TWS7 (0xB8) TWBR (0xB7) Reserved - (0xB6) ASSR - (0xB5) Reserved - (0xB4) OCR2B (0xB3) OCR2A (0xB2) ...

Page 10

Address Name Bit 7 (0x7D) Reserved - (0x7C) ADMUX REFS1 (0x7B) ADCSRB - (0x7A) ADCSRA ADEN (0x79) ADCH (0x78) ADCL (0x77) Reserved - (0x76) Reserved - (0x75) Reserved - (0x74) Reserved - (0x73) PCMSK3 PCINT31 (0x72) Reserved - (0x71) Reserved ...

Page 11

Address Name Bit 7 0x1B (0x3B) PCIFR - 0x1A (0x3A) Reserved - 0x19 (0x39) Reserved - 0x18 (0x38) Reserved - 0x17 (0x37) TIFR2 - 0x16 (0x36) TIFR1 - 0x15 (0x35) TIFR0 - 0x14 (0x34) Reserved - 0x13 (0x33) Reserved - ...

Page 12

Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

Page 13

Mnemonics Operands BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register ...

Page 14

Mnemonics Operands OUT P, Rr Out Port PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 2593NS–AVR–07/10 Description P ← Rr STACK ← Rr ...

Page 15

Ordering Information 6.1 ATmega644 (3) Speed (MHz) Power Supply 10 1.8V - 5.5V 20 2.7V - 5.5V Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information ...

Page 16

Packaging Information 7.1 44A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...

Page 17

A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm ...

Page 18

D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 2593NS–AVR–07/10 E Pin #1 Corner Pin #1 Option A 1 ...

Page 19

Errata 8.1 Rev. C • Inaccurate ADC conversion in differential mode with 200× gain 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC < 3.6V, random conversions will be inaccurate. Typical absolute accuracymay reach 64 LSB. ...

Page 20

Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 9.1 Rev. 2593N - 07/ ...

Page 21

Rev. 2593J - 09/ 9.6 Rev. 2593I - 08/ 9.7 Rev. 2593H - 07/ 9.8 Rev. 2593G - 06/ 9.9 Rev. 2593F - 04/06 ...

Page 22

Rev. 2593D - 04/ 9.12 Rev. 2593C - 03/ 9.13 Rev. 2593B - 03/ 10. 11. 12. 13. 14. 15. 16. 17. ...

Page 23

Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...

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