ATMEGA8A_09 ATMEL [ATMEL Corporation], ATMEGA8A_09 Datasheet
ATMEGA8A_09
Related parts for ATMEGA8A_09
ATMEGA8A_09 Summary of contents
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Features • High-performance, Low-power AVR • Advanced RISC Architecture – 130 Powerful Instructions – Most Single-clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – MIPS Throughput at 16 MHz – ...
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Pin Configurations Figure 1-1. 8159CS–AVR–07/09 Pinout ATmega8A PDIP (RESET) PC6 1 28 (RXD) PD0 2 27 (TXD) PD1 3 26 (INT0) PD2 4 25 (INT1) PD3 5 24 (XCK/T0) PD4 6 23 VCC 7 22 GND 8 21 (XTAL1/TOSC1) ...
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Overview The ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR RISC architec- ture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to ...
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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in ...
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Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil- lator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output ...
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... In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85° ...
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Register Summary Address Name Bit 7 0x3F (0x5F) SREG I 0x3E (0x5E) SPH – 0x3D (0x5D) SPL SP7 0x3C (0x5C) Reserved 0x3B (0x5B) GICR INT1 0x3A (0x5A) GIFR INTF1 0x39 (0x59) TIMSK OCIE2 0x38 (0x58) TIFR OCF2 0x37 (0x57) ...
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Register Summary (Continued) Address Name Bit 7 0x01 (0x21) TWSR TWS7 0x00 (0x20) TWBR Note: 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Instruction Set Summary (Continued) BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate LD Rd, X ...
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Instruction Set Summary (Continued) CLT Clear T in SREG SEH Set Half Carry Flag in SREG CLH Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset 8159CS–AVR–07/09 ATmega8A T ← 0 ...
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Ordering Information Speed (MHz) Power Supply (V) 16 2.7 - 5.5 Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging ...
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Packaging Information 8.1 32A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...
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A SEATING PLANE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 8159CS–AVR–07/09 ...
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Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R ...
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Errata The revision letter in this section refers to the revision of the ATmega8A device. 9.1 ATmega8A, rev. L • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the ...
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Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg- ister triggers an unexpected EEPROM interrupt ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section refers to the document revision. 10.1 Rev.8159C – 07/ 10.2 Rev.8159BS – 05/09 ...
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Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...