XC6108_1 TOREX [Torex Semiconductor], XC6108_1 Datasheet - Page 12

• Manufacturer Part Number: XC6108_1
• Description: Voltage Detector with Separated Sense Pin & Delay Type Capacitor
• Manufacturer: TOREX [Torex Semiconductor]

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■OPERATIONAL EXPLANATION
① As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged
② When the sense pin voltage keeps dropping and becomes equal to the detect voltage (V
③ While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground
④ When the sense pin voltage continues to increase up to the release voltage level (V
⑤ While the delay capacitance pin voltage (V
⑥ When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (V
⑦ While the sense voltage is higher than the detect voltage (V
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin voltage is V
As an example, presuming that the delay capacitance is 0.68μF, T
* Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the
* If a pull-up resistor of the XC6108N series (N-ch open drain) is connected to added power supply different from the input
to the power supply input voltage, (V
reach the detect voltage (V
(M3) for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An
inverter (Inv
(=V
(especially, when the Cd pin is not connected: T
voltage (=V
reach the release voltage (V
the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay
resistor (Rdelay). The inverter (Inv
Threshold: V
sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC
series circuit. Assuming the time to the release delay time (T
(Inv.1) will be inverted. As a result, the output voltage changes into the “High” (=V
which ranges from V
delay capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=V
level.
ground (=V
XC6108
voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected.
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on page 14.
SS
). The detect delay time [T
SS
SS
.
1) operates as a comparator of the reference voltage V
THL
) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to
) level because time described in ③ is short.
=V
SS
Series
SEN
) while the sense pin voltage keeps higher than the detect voltage (V
=V
DF
DF
SEN
) (V
+V
< V
HYS
SEN
* In = a natural logarithm
T
DF
IN /2
DF
DR
>V
to the V
IN
.
1) will operate as a comparator (Rise Logic Threshold: V
] is defined as time which ranges from V
+V
: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (V
DF
= − Rdelay × Cd × In (1 − V
(TYP.)
HYS
2.0e6 × 0.68e − 6 × 0.69 = 938 (ms)
), the output voltage (V
CD
OUT
).
T
) rises to reach the delay capacitance pin threshold voltage (V
DR
DF0
of “High” level without connecting to the Cd.
= 2.0e6 × Cd × 0.69…(2)
).
SEN
DR
OUT
), it can be given by the formula (1).
DR
> V
IN
TCD
is :
) keeps the “High” level (=V
, and the output voltage changes into the “Low” level
DF
/ V
), the delay capacitance pin is charged until the
IN
) …(1)
SEN
DF
+V
IN
=V
) level. T
HYS
DF
SEN
SEN
), the N-ch transistor (M3) for
to the V
> V
=V
IN
DF
SE
).
DF
DR0
CD
TLH
N
).
), an N-ch transistor
=V
OUT
) starts dropping to
=V
is defined as time
TCD
TCD
of “Low” level
), the inverter
TCD
, Fall Logic
) with the
IN
)