S-1112 SII [Seiko Instruments Inc], S-1112 Datasheet - Page 14

• Manufacturer Part Number: S-1112
• Description: HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
• Manufacturer: SII [Seiko Instruments Inc]

14
HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1112/1122 Series
Operation
2. Output transistor
1. Basic operation
Figure 12 shows the block diagram of the S-1112/1122 Series.
The error amplifier compares the reference voltage (V
divided by feedback resistors R
to ensure a certain output voltage free of any fluctuations of input voltage and temperature.
The S-1112/1122 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that V
to inverse current flowing from VOUT pin through a parasitic diode to VIN pin.
*1. Parasitic diode
VSS
VIN
OUT
Current
supply
does not exceed V
Reference voltage
V
ref
circuit
s
and R
−
+
amplifier
IN
Error
f
+ 0.3 V to prevent the voltage regulator from being damaged due
. It supplies the output transistor with the gate voltage necessary
Seiko Instruments Inc.
Figure 12
ref
) with V
R
R
s
f
fb
, which is the output voltage resistance-
V
*1
fb
VOUT
Rev.5.0
_00