71M6545 MAXIM [Maxim Integrated Products], 71M6545 Datasheet - Page 67

• Manufacturer Part Number: 71M6545
• Description: Four-Quadrant Metering, Phase Metrology Processors Flash/RAM Size
• Manufacturer: MAXIM [Maxim Integrated Products]

When system power is not available, the 71M6545/H will be in SLP mode, if a battery is attached to the
PDS_6545_009
3.2 SLP Mode (Sleep Mode)
Shortly after system power (V3P3SYS) is applied, the part will be in mission mode (MSN mode). MSN
mode means that the part is operating with system power and that the internal PLL is stable. This mode
is the normal operation mode where the part is capable of measuring energy.
VBAT_RTC pin.
Shortly after system power is removed (V3P3SYS < 3.0 VDC), VSTAT[2:0] will assume the value 001,
issuing a warning to the MPU. The IC can still operate in this state, however, the analog functions are not
considered accurate. Assuming that the recommended MPU setup code is resident in flash memory (see
2.4.1 MPU Setup Code
by the MPU setting the SLEEP bit (I/O RAM 0x28B2[7]).
When system power is restored, the 71M6545/H will automatically transition from SLP mode back to MSN
mode.
The SLP mode may be commanded by the MPU whenever main system power is absent by asserting the
SLEEP bit. The purpose of the SLP mode is to consume the least power while still maintaining the RTC,
temperature compensation of the RTC, and the non-volatile portions of the I/O RAM.
In SLP mode, the V3P3D pin is disconnected, removing all sources of leakage from V3P3SYS. The non-
volatile memory domain and the basic functions, such as temperature sensor, oscillator, and RTC, are
powered by the VBAT_RTC input. In this mode, the I/O configuration bits and NV RAM values are
preserved and RTC and oscillator continue to run. This mode can be exited only by system power up.
v1.0
CE
FIR
ADC, VREF
PLL
Battery measurement
Temperature sensor
Maximum MPU clock rate
MPU_DIV clock divider
ICE
DIO Pins
Watchdog Timer
V3P3D Pin
VDD Pin
EEPROM Interface (2-wire)
EEPROM Interface (3-wire)
UART (full speed)
SPI slave port
SPI Special Flash Mode
Optical TX modulation
Flash Read
Flash Page Erase
Flash Write
RAM Read and Write
OSC and RTC
RAM data preservation
NV RAM data preservation
on page 30), at V3P3SYS < 2.8 VDC, the 71M6545/H will be forced to SLP mode
Circuit Function
© 2008–2011 Teridian Semiconductor Corporation
Table 55: Available Circuit Functions
– indicates not active
System Power
(from PLL)
4.92MHz
MSN
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Battery Power
SLP
Yes
Yes
Yes
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Data Sheet 71M6545/H
67