A3P060-1VQ144T ACTEL [Actel Corporation], A3P060-1VQ144T Datasheet - Page 74

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A3P060-1VQ144T

Manufacturer Part Number
A3P060-1VQ144T
Description
Automotive ProASIC3 Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
Automotive ProASIC3 DC and Switching Characteristics
Figure 2-21 • Input DDR Timing Diagram
Table 2-99 • Input DDR Propagation Delays
2 -6 2
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
Out_QR
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
Out_QF
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage supply levels, refer to
values.
Timing Characteristics
Automotive-Case Conditions: T
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
Data Hold for Input DDR
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
t
t
1
DDRICLR2Q2
DDRICLR2Q1
t
DDRIREMCLR
2
3
t
DDRICLKQ1
J
= 135°C, Worst-Case V
Description
4
2
v1.0
3
5
t
DDRICLKQ2
CC
t
DDRISUD
6
= 1.425 V
4
5
Table 2-5 on page 2-5
7
t
DDRIHD
0.33
0.47
0.34
0.00
0.56
0.69
0.00
0.27
0.25
0.41
0.37
TBD
t
8
–1
DDRIRECCLR
6
7
0.39
0.56
0.40
0.00
0.66
0.82
0.00
0.32
0.30
0.48
0.43
TBD
Std.
for derating
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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