TMC428-A ETC2 [List of Unclassifed Manufacturers], TMC428-A Datasheet - Page 30

• Manufacturer Part Number: TMC428-A
• Description: Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

TMC428 DATASHEET (v. 2.02 / April 26
3
1
Table 9-1: Stepper motor global parameter register
Table 9-2: Global parameter LSMD (last stepper motor driver)
Five bits are used to control signal polarities. The polarity of the selection signal nSCS_S for the
stepper motor driver chain is controlled by the polarity bit polarity_nscs_s. The nSCS_S signal is low
active if this bit is set to ‘0’ and it is high active, if this bit is set to ‘1’.
The polarity of the stepper motor driver chain clock signal SCK_S is defined by the bit polarity_sck_s.
If this bit is ‘0’, the clock polarity is according to Figure 6-3 on page 10. The clock signal SCK_S is
inverted if it is set to ‘1’. The bit polarity_PH_AB defines the polarity of the phase bits for the stepper
motor. Inverting this bit changes the rotation direction of the associated stepper motor. The bit
polarity_FD defines the polarity of the fast decay controlling bit. If it is ‘0’ fast decay is high active and
if it is ‘1’ fast decay is low active. The bit named polarity_DAC_AB defines the polarity of the DAC bit
vectors. If it is ‘0’ the DAC bits are high active and if it is ‘1’ the DAC bits are inverted – low active.
The bit named csCommonIndividual defines either if a single chip select signal nSCS_S is used in
common for all stepper motor driver chips (TMC236, TMC239, TMC246, TMC249) or three chip select
signals nSCS_S, nSCS2, nSCS3 are used to select the stepper motor driver chips individually. This
feature is useful only for the TMC428 within the larger packages, where the two additional chip select
signals nSCS2, nSCS3 are available (see Figure 2-2). The one common chip select signal nSCS_S is
used if the bit named csCommonIndividual=‘0’. The polarity control bit for the nSCS_S signal must
be set to polarity_nscs_s=’0’ if csCommonIndividual=’1’. The chip select polarity is always negative
for three individual chips select signals.
The eight bits named clk2_div determine the clock frequency of the stepper motor driver chain clock
signal SCK_S. The frequency f_sck_s[Hz] of the stepper motor driver chain clock signal SCK_S is
f_sck_s[Hz] = f_clk[Hz] / ( 2 * (clk2_div+1) ). A value of 255 (%11111111, $FF) is the upper limit for
the parameter clk2_div. With clk2_div = 255 the clock frequency of SCK_S is at minimum. Due to
internal processing, a value of 7 (%00000111, $07) is the lower limit for the clock divider parameter
Copyright © 2004-2006, TRINAMIC Motion Control GmbH & Co. KG
0
3
0
1 1 1 1 1 1
%00 (=0)
%01 (=1)
%10 (=2)
%11 (=3)
LSMD
2
9
ADDRESS
2
8
2
7
2
6
2
5
2
4
32 bit DATAGRAM sent from a µC to the TMC428
number of stepper motor drivers
2
3
2
2
2
1
NOT ALLOWED
2
0
1
9
1
2
3
th
, 2006)
1
8
1
7
1
6
1
5
1
4
1
3
clk2_div
DATA
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
polarities
LSMD
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