HT82M99E-18 HOLTEK [Holtek Semiconductor Inc], HT82M99E-18 Datasheet
HT82M99E-18
Related parts for HT82M99E-18
HT82M99E-18 Summary of contents
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... General Description The USB MCU OTP body is suitable for USB mouse and USB joystick devices. It consists of a Holtek high Block Diagram Rev. 1.50 HT82M99E USB Mouse Encoder 8-Bit OTP MCU 96 bytes RAM (20H~7FH) 6MHz/12MHz internal CPU clock 4-level stacks Two 7-bit indirect addressing registers ...
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... USBD+ or PS2 CLK I/O line USB or PS2 function is controlled by software control register USBD- or PS2 DATA I/O line USB or PS2 function is controlled by software control register OSCI, OSCO are connected to a 6MHz or 12MHz crystal/resonator (de- termined by software instructions) for the internal system clock. 2 HT82M99E November 19, 2004 ...
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... =3.4V 2 2.4 Test Conditions Min. V Conditions Without WDT prescaler 1024 75 Wake-up from HALT 256 WDTS+t WDT 256 WDTS+t +t SST OSC 3 HT82M99E Ta=25 C Typ. Max. Unit 5 300 500 4.7 6 ...
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... PC Program Counter S10~S0: Stack register bits @7~@0: PCL bits 4 HT82M99E * November 19, 2004 ...
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... TBLP and the current program counter bits. Table Location * Table Location P10~P8: Current program counter bits when TBHP is disabled TBHP register bit2~bit0 when TBHP is enabled 5 HT82M99E * November 19, 2004 ...
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... All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i . They are also indirectly accessible through memory pointer registers (MP0 or MP1). 6 HT82M99E November 19, 2004 ...
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... RAM Bank 1 Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers Rev. 1.50 HT82M99E Indirect Addressing Register Locations 00H and 02H are indirect addressing regis- ters that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1) ...
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... Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. Function INTC Register 8 HT82M99E November 19, 2004 ...
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... ROM code option. This timer is designed to prevent a software malfunction 0CH or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be dis- abled by ROM code option. If the Watchdog Timer is dis- 9 HT82M99E November 19, 2004 ...
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... If the interrupt is enabled and the stack is not full, the regular interrupt re- sponse takes place interrupt request flag is set to 1 before entering the HALT mode, the wake-up func- tion of the related interrupt will be disabled. Once a 10 HT82M99E November 19, 2004 ...
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... HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. Rev. 1.50 HT82M99E Reset Timing Chart Reset Circuit Reset Configuration The functional unit chip reset status are shown below. ...
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... HT82M99E USB-Reset (HALT) uuuu uuuu uuuu uuuu 00-0 1--- 00-0 1--- 000H 000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu ...
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... In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON Function TMRC Register Timer/Event Counter 13 HT82M99E /4 SYS /4. SYS November 19, 2004 ...
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... It should be noted that a non-pull-high/low I/O line operating in input mode will cause a floating state recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Input/Output Ports 14 HT82M99E November 19, 2004 ...
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... A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode. Rev. 1.50 The relationship between must LVR Note the voltage range for proper chip opera- OPR tion at 6MHz or 12MHz system clock. Low Voltage Reset 15 HT82M99E and V is shown below. LVR November 19, 2004 ...
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... Not this function 1: The function exists Bit7~Bit2 Reserved Bit 1 Pipe 1 Pipe 1 Pipe 1 Stall and Pipe Registers Read/Write R R/W R/W R/W SIES Registers Table 16 HT82M99E FIFO 0 FIFO 1 48H 49H Bit 0 Default Bit 0 Value Pipe 0 00000011 Pipe 0 00000000 Pipe 0 00000000 Register Address 01000101B November 19, 2004 ...
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... The Misc register is actually a command + status to control the desired FIFO action and to show the status of the de- sired FIFO. Every bit s meaning and usage are listed as follows: Bit No. Function 7 Len0 6 Ready 5 Set CMD 4 Sel_pipe1 3 Sel_pipe0 2 Clear Request Rev. 1.50 Description SIES Function Table Read/Write Register Address R/W R R/W R/W R/W R/W R/W R/W Misc Registers Table 17 HT82M99E 01000110B November 19, 2004 ...
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... Set MISC TX bit = 0 Clear the REQ bit to 0. Complete writing. User writes the data through the FIFO pointer register, user has to record the number of bytes that have been written. The HT8M99E allows a maximum of 8 bytes of data in each packet. 18 HT82M99E November 19, 2004 ...
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... So when the MCU is detecting the Suspend line (bit0 of the USC), the Resume line should be remem- bered and taken into consideration. After finishing the resume signal, the suspend line will go inactive and a USB interrupt is triggered. The follow- ing is the timing diagram: 19 HT82M99E Bit7~Bit0 Data7~Data0 Data7~Data0 November 19, 2004 ...
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... I/O (R/W), has pull-low and pull-high option, ADC input. I/O (R/W), has pull-low and pull-high option, ADC input. I/O (R/W), has pull-high option, can wake-up, ADC input. Reserved bit. I/O (R/W), has pull-high option, ADC input, VRH input for ADC ex- ternal mode, has wake-up capability. 20 HT82M99E November 19, 2004 ...
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... When set indicates that the chip is working under SELUSB USB mode. Default value is 0. Reserved bit, set to 0 This flag is used to show that the MCU is in USB mode (Bit=1). This bit is R and will be cleared to zero USB_flag after power-on reset. The default HT82M99E November 19, 2004 ...
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... Operating at external 6MHz mode Default value This flag is used to show that the MCU is in PS2 mode PS2_flag (Bit=1). This bit is R and will be cleared to zero after power-on reset. The default Option Functions Store current table read bit10~bit8 data Option 22 HT82M99E November 19, 2004 ...
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... Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Rev. 1.50 HT82M99E 23 November 19, 2004 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.50 Instruction Description 24 HT82M99E Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ROM code TBHP option is enabled (6) : ROM code TBHP option is disabled Rev. 1.50 Instruction Description 25 HT82M99E Flag Cycle Affected 2 None (2) 1 None (2) 1 ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 1. HT82M99E November 19, 2004 ...
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... Operation Stack PC+1 PC addr Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 1. HT82M99E November 19, 2004 ...
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... Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 1. HT82M99E November 19, 2004 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 1. (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C HT82M99E November 19, 2004 ...
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... Operation PC addr Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 1. HT82M99E November 19, 2004 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 1. HT82M99E November 19, 2004 ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 1. HT82M99E November 19, 2004 ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 1. HT82M99E November 19, 2004 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev HT82M99E November 19, 2004 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 1. ([m]+ ([m]+ HT82M99E November 19, 2004 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 1. [m].7~[m].4 [m].3~[m]. HT82M99E November 19, 2004 ...
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... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 1. HT82M99E November 19, 2004 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 1. HT82M99E November 19, 2004 ...
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... Package Information 18-pin DIP (300mil) Outline Dimensions Symbol Min. A 895 B 240 C 125 D 125 295 I 335 0 Rev. 1.50 HT82M99E Dimensions in mil Nom. Max. 915 260 135 145 20 70 100 315 375 15 39 November 19, 2004 ...
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... DIP (300mil) Outline Dimensions Symbol Min. A 1020 B 240 C 125 D 125 295 I 335 0 Rev. 1.50 HT82M99E Dimensions in mil Nom. Max. 1045 260 135 145 20 70 100 315 375 15 40 November 19, 2004 ...
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... SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 C 14 447 Rev. 1.50 HT82M99E Dimensions in mil Nom. Max. 419 300 20 460 104 November 19, 2004 ...
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... SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 C 14 490 Rev. 1.50 HT82M99E Dimensions in mil Nom. Max. 419 300 20 510 104 November 19, 2004 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 18W, SOP 20W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.50 HT82M99E Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 43 November 19, 2004 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.50 HT82M99E Dimensions in mm 24+0.3 0.1 16 0.1 1.75 0.1 11.5 0.1 1.5 0.1 1.5+0.25 4 0.1 2 0.1 10.9 0.1 12 0.1 2.8 0.1 0.3 0.05 21.3 Dimensions in mm 24+0.3 0.1 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.50 HT82M99E 45 November 19, 2004 ...