HT82M9BAE HOLTEK [Holtek Semiconductor Inc], HT82M9BAE Datasheet
HT82M9BAE
Related parts for HT82M9BAE
HT82M9BAE Summary of contents
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... USB joystick devices. It consists of a Holtek high performance 8-bit MCU core for control unit, built-in USB SIE ROM and 224 bytes data RAM. The mask version HT82M9BAE is fully pin and function- ally compatible with the OTP version HT82M9BEE device. Rev. 1.20 ...
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... Block Diagram Pin Assignment Rev. 1.20 HT82M9BEE/HT82M9BAE 2 August 13, 2007 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.20 HT82M9BEE/HT82M9BAE Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is con- trolled by PAC (PA control register) ...
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... System Start-up Timer Period SST t Crystal Setup OSC Note: Power-on period WDT SST OSC WDT Time-out in normal mode=1/f WDT Time-out in HALT mode=1/f Rev. 1.20 HT82M9BEE/HT82M9BAE Test Conditions V Conditions DD No load, f =6MHz 5V SYS No load, f =12MHz 5V SYS 5V No load, system HALT, USB suspend ...
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... SCL Pins) t Write Cycle Time WR Note: These parameters are periodically sampled but not 100% tested * The standard mode means V CC For relative timing, refer to timing diagrams Rev. 1.20 HT82M9BEE/HT82M9BAE Standard Mode* Remark Min. 4000 4700 Note Note After this period the first ...
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... S12 S11 S10 Note: *12~*0: Program counter bits #12~#0: Instruction code bits Rev. 1.20 HT82M9BEE/HT82M9BAE After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. ...
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... TABRDL [ Note: *12~*0: Table location bits @7~@0: TBLP bits Rev. 1.20 HT82M9BEE/HT82M9BAE Table location Any location in the program memory can be used as look-up tables. There are three method to read the ROM data by two table read instructions: TABRDC and TABRDL , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H) ...
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... The RAM bank 1 mapping is as shown. Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers Rev. 1.20 HT82M9BEE/HT82M9BAE Bank 0 RAM Mapping Indirect Addressing Register Locations 00H and 02H are indirect addressing regis- ters that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1) ...
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... Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions. The ALU provides the following functions: Rev. 1.20 HT82M9BEE/HT82M9BAE Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, OR, XOR, CPL) Rotation (RL, RR, RLC, RRC) Increment and Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ ...
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... HT82M9BEE/HT82M9BAE receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT82M9BEE/HT82M9BAE is set and a USB interrupt is also triggered. When the HT82M9BEE/HT82M9BAE receives a Re- ...
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... OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The HT82M9BEE/HT82M9BAE can operate in 6MHz or 12MHz system clocks. In order to make sure that the USB SIE functions properly, user should correctly con- figure the SCLKSEL bit of the SCC Register ...
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... All of the I/O ports remain in their original status. The PDF flag is set and the TO flag is cleared. Rev. 1.20 HT82M9BEE/HT82M9BAE The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig- nal on port WDT overflow. An external reset causes a device initialization and the WDT overflow per- forms a warm reset ...
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... WDTS 1000 0111 1000 0111 STATUS --00 xxxx --1u uuuu INTC -000 0000 -000 0000 TMR0 xxxx xxxx 0000 0000 Rev. 1.20 HT82M9BEE/HT82M9BAE Reset Circuit Reset Timing Chart Reset Configuration RES Reset WDT RES Reset (Normal Time-out (HALT) Operation) (HALT)* 000H 000H ...
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... Using the internal clock source, there is only 1 reference time-base for Timer/Event Counter 0. The internal clock source is coming from f /4. SYS Rev. 1.20 HT82M9BEE/HT82M9BAE RES Reset WDT RES Reset (Normal Time-out (HALT) Operation) (HALT)* ...
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... TM1 11=Pulse width measurement mode 00=Unused Rev. 1.20 HT82M9BEE/HT82M9BAE In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR0/TMR1 has re- ceived a transient from low to high (or high to low if the TE bits will start counting until the TMR0/TMR1 returns to the original level and resets the TON. The measured result will remain in the Timer/Event Counter 0/1 even if the activated transient occurs again ...
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... PA to PC, which are mapped to the data memory of [12H], [14H] and [16H] respectively. All of these I/O ports can be used for input Rev. 1.20 HT82M9BEE/HT82M9BAE Timer/Event Counter 0 Timer/Event Counter 1 and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 16H) ...
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... A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode. Rev. 1.20 HT82M9BEE/HT82M9BAE Low Voltage Reset - LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device drops to within the range of 0 ...
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... EEPROM sends a zero to acknowledge that it has re- ceived each word. This happens during the ninth clock cycle. Rev. 1.20 HT82M9BEE/HT82M9BAE Device Addressing The 1K EEPROM devices all require an 8-bit device ad- dress word following a start condition to enable the chip for a read or write operation. The device address word ...
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... The address roll over during write from the Rev. 1.20 HT82M9BEE/HT82M9BAE last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and ac- knowledged by the EEPROM, the current address data word is serially clocked out ...
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... DATA0, the user can output a LOW pulse to this bit. The LOW pulse period must at least 10 instruction cycle. Endpt_EN register is used to enable or disable the corresponding endpoint (except endpoint 0). Enable Endpoint (Bit=1) or disable Endpoint (Bit=0). Rev. 1.20 HT82M9BEE/HT82M9BAE SIES MISC Endpt_EN FIFO0 45H 46H ...
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... End of transient flag, normal status suspend= 1 line & EOT= 0 indicates that EOT R something is wrong in the USB Interface. The programmer must do something to save the device and keep it alive. MNI R/W This bit is for masking the NAK interrupt when MNI the default value= 0 Rev. 1.20 HT82M9BEE/HT82M9BAE Bit 3 Bit 2 Bit 1 Pipe 3 Pipe 2 Pipe 1 Pipe 3 Pipe 2 ...
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... Tx R/W R/W MISC (46H) Registers Table Description MISC Function Table The HT82M9BEE/HT82M9BAE allows a maximum of 8 bytes of data in each packet. The HT82M9BEE/HT82M9BAE FIFO is written by packet. To write to FIFO, the following should be fol- lowed: Select a set of FIFO, set in the write mode (MISC TX bit = 1), and set the REQ bit to 1 ...
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... When the resume signal is sent out by the host, the HT82M9BEE/HT82M9BAE will wake-up the MCU by USB interrupt and the Resume line (bit 3 of the USC) is set. In order to make the HT82M9BEE/HT82M9BAE function properly, the programmer must set the USBCKEN (bit 3 of the SCC and clear the SUSP2 (bit4 of the SCC) ...
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... PS2DAI, the PS2DAO should be set Oth- erwise it always read HT82M9BAE is defined as a USB interface. Both the USBD- and USBD+ are driven by the USB SIE of the HT82M9BEE/HT82M9BAE. User only writes or reads the USB data through the corresponding FIFO ...
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... PEC4 R/W 5 PEC5 R/W 6 PEC6 R/W 7 PEC7 R/W Rev. 1.20 HT82M9BEE/HT82M9BAE Option Functions I/O (R/W), has pull-high option Reserved PC (16H) Register Option Functions USB suspend mode status bit. When 1, indicates that the USB SUSPEND system entry is in suspend mode. RMOT_WK USB remote wake-up signal. The default value ...
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... CLR WDT , instructions 10 TBHP enable/disable (default: disable output mode (CMOS/NMOS/PMOS) by bit (default: CMOS) Rev. 1.20 HT82M9BEE/HT82M9BAE Option Functions Reserved, must set USB clock control bit. When set indicates a USBCK ON, USBCKEN else USBCK OFF. The default value This bit is used to reduce power consumption in the suspend mode ...
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... RES high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application. Rev. 1.20 HT82M9BEE/HT82M9BAE 27 August 13, 2007 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.20 HT82M9BEE/HT82M9BAE Description 28 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ROM code TBHP option is enabled (6) : ROM code TBHP option is disabled Rev. 1.20 HT82M9BEE/HT82M9BAE Description 29 Instruction Flag Cycle Affected 2 ...
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... ACC+x Affected flag(s) TO ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF PDF PDF PDF ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF PDF PDF addr PDF OV Z ...
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... Affected flag( CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF PDF PDF OV ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE Program Counter+1 PDF PDF PDF ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF PDF Program Counter+1 ...
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... Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE Stack PDF Stack PDF ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF OV ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF PDF OV Z ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF PDF ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF PDF PDF ...
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... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF PDF PDF ...
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... XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.20 HT82M9BEE/HT82M9BAE PDF PDF PDF OV ...
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... Package Information 24-pin SOP (300mil) Outline Dimensions Symbol Rev. 1.20 HT82M9BEE/HT82M9BAE Dimensions in mil Min. Nom. 394 290 14 590 Max. 419 300 20 614 104 August 13, 2007 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.20 HT82M9BEE/HT82M9BAE Dimensions in mil Min. Nom. 394 290 14 697 Max. 419 300 20 713 104 August 13, 2007 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SOP 28W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.20 HT82M9BEE/HT82M9BAE Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 45 August 13, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.20 HT82M9BEE/HT82M9BAE Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.55+0.1 1.5+0.25 4 0.1 2 0.1 10.9 0.1 15.9 0.1 3.1 0.1 0.35 0.05 21.3 Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 HT82M9BEE/HT82M9BAE 47 August 13, 2007 ...