HN58X2402SFPIAG RENESAS [Renesas Technology Corp], HN58X2402SFPIAG Datasheet
HN58X2402SFPIAG
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HN58X2402SFPIAG Summary of contents
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... Shipping tape and reel: 2,500 IC/reel • Lead free products. 2 Note trademark of Philips Corporation. Ordering Information Type No. Internal organization 2k bit (256 × 8-bit) HN58X2402SFPIAGE 4k bit (512 × 8-bit) HN58X2404SFPIAGE Rev.4.00, Jul.13.2005, page serial bus* ) Operating voltage 1 5.5 V REJ03C0133-0400 Rev ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Pin Arrangement Pin Description Pin name SCL SDA Block Diagram A0, A1, A2 SCL SDA Absolute Maximum Ratings Parameter Supply voltage relative Input voltage relative Operating temperature range* Storage temperature range Notes: 1. Including electrical characteristics and data retention. ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG DC Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Operating temperature (min): −1.0 V for pulse width ≤ 50 ns. Note (Ta = −40 to +85° Characteristics Parameter Symbol Input leakage current I LI Output leakage current I LO Standby V current ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG (Ta = −40 to +85° Characteristics Test Conditions • Input pules levels: 0.2 × 0.8 × • Input rise and fall time: ≤ • Input and output timing reference levels: 0.5 × V • Output load: TTL Gate + 100 pF Parameter ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Timing Waveforms Bus Timing t F SCL t SU.STA SDA (in) SDA (out) t SU.WP WP Write Cycle Timing SCL D0 in SDA Write data (Address (n)) Rev.4.00, Jul.13.2005, page 1/f SCL t t LOW HIGH t HD.DAT t HD.STA Stop condition ACK (Internally controlled SU.DAT SU ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz. Serial Input/Output data (SDA) The SDA pin is bidirectional for serial data transfer ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Device Address (A0, A1, A2 eight devices for 2k, four devices for 4k, can be addressed on the same bus by setting the levels on these pins to different combinations. The levels on these pins are compared with the device address code which are input through the SDA pin. The device is selected if the compare is successfully done. These pins are internally pulled-down to V The device read these pins as Low if unconnected ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation. (See start condition and stop condition) Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and this EEPROM uses “ ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Write Operations Byte Write: A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, EEPROMs receive 8-bit memory address word. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment " ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM internally-timed write cycle or not. This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “0”. ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word(R/W is “ ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word(R/W=0) and memory address sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgment “ ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Notes Data protection at V On/Off CC When V is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. • ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Package Dimensions HN58X2402SFPIAGE / HN58X2404SFPIAGE (PRSP0008DF-B / Previous Code: FP-8DBV) JEITA Package Code RENESAS Code P-SOP8-3.9x4.89-1.27 PRSP0008DF Index mark Rev.4.00, Jul.13.2005, page Previous Code MASS[Typ.] FP-8DBV 0.08g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. ...
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... HN58X2402SFPIAG/HN58X2404SFPIAG Contents of Modification Initial issue Change format issued by Renesas Technology Corp. Ordering Information Addition of HN58X2402SFPIAGE, HN58X2404SFPIAGE Package Dimensions FP-8DB to FP-8DB, FP-8DBV Ordering Information Deletion of HN58X2402SFPIAG, HN58X2404SFPIAG Package Dimensions Deletion of FP-8DB Ordering Information Addition of Renesas package codes AC Characteristics Addition of t HD.WP Addition of t SU.WP Timing Waveforms ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...