A29L004UW-70 AMICC [AMIC Technology], A29L004UW-70 Datasheet

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A29L004UW-70

Manufacturer Part Number
A29L004UW-70
Description
512K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Manufacturer
AMICC [AMIC Technology]
Datasheet
Preliminary
Features
n Single power supply operation
n Access times:
n Current:
n Flexible sector architecture
n Unlock Bypass Program Command
n Top or bottom boot block configurations available
n Embedded Algorithms
PRELIMINARY
- Embedded Program algorithm automatically writes
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
- Full voltage range: 2.7 to 3.6 volt read and write
- Regulated voltage range: 3.0 to 3.6 volt read and write
- 70/90 (max.)
- 4 mA typical active read current
- 20 mA typical program/erase current
- Reduces overall programming time when issuing
- Embedded Erase algorithm will automatically erase
operations for battery-powered applications
operations for compatibility with high performance 3.3
volt microprocessors
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector. Temporary Sector Unprotect feature
allows code changes in previously locked sectors
multiple program command sequence
the entire chip or any combination of designated
sectors and verify the erased sectors
and verifies data at specified addresses
(October, 2002, Version 0.0)
1
n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125 C
n Compatible with JEDEC-standards
n
n Ready /
n Erase Suspend/Erase Resume
n Hardware reset pin (
n Package options
512K X 8 Bit CMOS 3.0 Volt-only,
- Reliable operation for the life of the system
- Pinout and software compatible with single-power-
- Superior inadvertent write protection
- Provides a software method of detecting completion
- Provides a hardware method of detecting completion
- Suspends a sector erase operation to read data from,
- Hardware method to reset the device to reading array
- 40-pin TSOP (forward type), 32-pin PLCC or (s)TSOP
Data
supply Flash memory standard
of program or erase operations (not available on 32-
pin PLCC & (s)TSOP packages)
data (not available on 32 pin PLCC & (s)TSOP
packages)
of program or erase operations
(forward type)
or program data to, a non-erasing sector, then
resumes the erase operation
Polling and toggle bits
Boot Sector Flash Memory
BUSY
pin (RY /
A29L004 Series
RESET
AMIC Technology, Corp.
BY
)
)

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A29L004UW-70 Summary of contents

Page 1

Preliminary Features n Single power supply operation - Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications - Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 ...

Page 2

General Description The A29L004 is a 4Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes of 8 bits. The 8 bits of data appear on I/O - I/O . The A29L004 is offered in 40-pin 0 7 TSOP, 32-pin PLCC ...

Page 3

Pin Configurations A16 1 A15 2 A14 3 A13 4 A12 5 A11 RESET RY/BY 12 A18 ...

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Block Diagram RY/BY (N/A 32-pin PLCC, (s)TSOP) VCC VSS RESET (N/A 32-pin PLCC, (s)TSOP) State Control WE Command Register CE OE VCC Detector A0-A18 Pin Descriptions Pin No A18 I/O RESET RY/ PRELIMINARY (October, 2002, Version 0.0) Sector ...

Page 5

Absolute Maximum Ratings* Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE and OE pins the power control and IL selects the device the output control and ...

Page 7

RESET : Hardware Reset Pin (N/A on 32-pin PLCC & (s)TSOP packages) The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period ...

Page 8

Table 2. A29L004 Top Boot Block Sector Address Table Sector A18 A17 SA0 0 0 SA1 0 0 SA2 0 1 SA3 0 1 SA4 1 0 SA5 1 0 SA6 1 1 SA7 1 1 SA8 1 1 SA9 ...

Page 9

Table 4. A29L004 Autoselect Codes (High Voltage Method) Description CE Manufacturer ID: AMIC L Device ID: A29L004 L (Top Boot Block) Device ID: A29L004 L (Bottom Boot Block) Continuation ID L Sector Protection Verification L L=Logic Low H=Logic ...

Page 10

Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors possible to determine whether a sector is ...

Page 11

START PLSCNT=1 RESET=V ID Wait Temporary Sector First Write Unprotect Mode Cycle=60h? Yes Set up sector address Sector Protect Write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 us Verify Sector Protect: Write 40h to ...

Page 12

Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence ...

Page 13

START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data ? Increment Address Last Address ? Programming Completed Note : See the appropriate Command Definitions table for program command sequence. Figure 3. Program Operation ...

Page 14

Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor I/O . Any command other than Sector ...

Page 15

Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Manufacturer ID 4 Device ID, 4 Top Boot Block Device ID, 4 Bottom Boot Block Continuation ID 4 Sector Protect Verify 4 (Note 9) Program 4 Unlock Bypass ...

Page 16

Write Operation Status Several bits, I/O , I/O , I/O , I the A29L004 to determine the status of a write operation (RY/ BY pin is not available on 32-pin PLCC & (s)TSOP ...

Page 17

BY : Read/ Busy (N/A on 32-pin PLCC & (s)TSOP RY/ packages) The RY dedicated, open-drain output pin that indicates whether an Embedded algorithm is in progress or complete. The RY/ BY status is valid after the ...

Page 18

I/O : Exceeded Timing Limits 5 I/O indicates whether the program or erase time has 5 exceeded a specified internal pulse count limit. Under these conditions I/O produces a "1." This is a failure condition 5 that indicates the program ...

Page 19

Operation Standard Embedded Program Algorithm Mode Embedded Erase Algorithm Erase Reading within Erase Suspend Suspended Sector Mode Reading within Non-Erase Suspended Sector Erase-Suspend-Program Notes: 1. I/O and I/O require a valid address when reading status information. Refer to the appropriate ...

Page 20

DC Characteristics CMOS Compatible Parameter Parameter Description Symbol I Input Load Current Input Load Current LIT I Output Leakage Current LO VCC Active Read Current I CC1 (Notes 1, 2) VCC Active Write (Program/Erase) I CC2 Current ...

Page 21

DC Characteristics (continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1MHz I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note ...

Page 22

AC Characteristics Read Only Operations Parameter Symbols JEDEC Std t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE Output Enable to Output Delay ...

Page 23

AC Characteristics Hardware Reset ( RESET N/A on 32-pin PLCC & (s)TSOP packages) , Parameter JEDEC Std RESET Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET Pin Low (Not During Embedded t READY Algorithms) ...

Page 24

Temporary Sector Unprotect (N/A on 32-pin PLCC & (s)TSOP packages) Parameter JEDEC Std t V Rise and Fall Time (See Note) VIDR ID RESET Setup Time for Temporary Sector t RSP Unprotect Note: Not 100% tested. Temporary Sector Unprotect Timing ...

Page 25

AC Characteristics Erase and Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH DS t ...

Page 26

Timing Waveforms for Program Operation Program Command Sequence (last two cycles Addresses 555h Data RY/BY t VCS VCC Note : program addrss program data, Dout is the true ...

Page 27

Timing Waveforms for Chip/Sector Erase Operation Erase Command Sequence (last two cycles Addresses 2AAh Data RY/BY t VCS VCC Note : Sector Address (for Sector Erase Valid Address ...

Page 28

Timing Waveforms for Data Polling (During Embedded Algorithms Addresses VA t ACC OEH WE I/O 7 I/O - I/O High BUSY RY/BY Note : VA = Valid Address. ...

Page 29

Timing Waveforms for Toggle Bit (During Embedded Algorithms Addresses VA t ACC OEH WE I/O , I/O High BUSY RY/BY Note Valid Address; not required for ...

Page 30

Timing Waveforms for Sector Protect/Unprotect RESET SA, A6, A1, A0 Sector Protect/Unprotect 60h Data 1us Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0 PRELIMINARY (October, 2002, Version ...

Page 31

Timing Waveforms for I/O vs. I/O 2 Enter Erase Embedded Suspend Erasing WE Erase Erase Suspend I/O 6 I/O 2 I/O and I/O toggle with OE and Note : Both I/O and I/O toggle with OE or ...

Page 32

Timing Waveforms for Alternate CE Controlled Write Operation 555 for program 2AA for erase Addresses Data for program 55 for erase RESET RY/BY Note : 1. ...

Page 33

Latch-up Characteristics Input Voltage with respect to VSS on all I/O pins VCC Current Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET ) Includes all pins except VCC. Test conditions: VCC ...

Page 34

Test Conditions Test Specifications Test Condition Output Load Output Load Capacitance, C (including jig capacitance) L Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Device Under Test PRELIMINARY ...

Page 35

... A29L004TL-70 A29L004TX-70 70 A29L004TV-70 A29L004TW-70 A29L004TL-90 A29L004TX-90 90 A29L004TV-90 A29L004TW-90 Bottom Boot Sector Flash Access Time Part No. (ns) A29L004UL-70 A29L004UX-70 70 A29L004UV-70 A29L004UW-70 A29L004UL-90 A29L004UX-90 90 A29L004UV-90 A29L004UW-90 PRELIMINARY (October, 2002, Version 0.0) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA Active Read Program/Erase ...

Page 36

Package Information TSOP 40L TYPE I (10 X 20mm) Outline Dimensions Pin1 Symbol Notes: 1. Dimension D 2. The lead width dimension does not include dambar protrusion. ...

Page 37

Package Information PLCC 32L Outline Dimension Symbol Notes: 1. Dimensions ...

Page 38

Package Information TSOP 32L TYPE 20mm) Outline Dimensions y Symbol Notes: 1. The maximum value of dimension D includes end ...

Page 39

Package Information sTSOP 32L TYPE 14mm) Outline Dimensions Pin1 Symbol Notes: 1. Dimension E does not include mold flash. 2. Dimension D 3. ...

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