HN58X24128FPIAG RENESAS [Renesas Technology Corp], HN58X24128FPIAG Datasheet
HN58X24128FPIAG
Related parts for HN58X24128FPIAG
HN58X24128FPIAG Summary of contents
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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... HN58X24128FPIAG HN58X24256FPIAG 128k EEPROM (16-kword 256k EEPROM (32-kword Description HN58X24xxxFPIAG series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. ...
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... Shipping tape and reel: 2,500 IC/reel Temperature range: – Note trademark of Philips Corporation. Ordering Information Type No. Internal organization Operating voltage Frequency HN58X24128FPIAG 128k bit (16384 8-bit) HN58X24256FPIAG 256k bit (32768 8-bit) Pin Arrangement Pin Description Pin name ...
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... Vin (min): –3.0 V for pulse width 3. Should not exceed Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Operating temperature Notes (min): –1.0 V for pulse width IL HN58X24128FPIAG/HN58X24256FPIAG Control logic Symbol Value V –0 Vin –0.5* Topr –40 to +85 Tstg – ...
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... HN58X24128FPIAG/HN58X24256FPIAG DC Characteristics (Ta = –40 to +85˚C, V Parameter Symbol Input leakage current I LI Output leakage current I LO Standby V current Read V current I CC CC1 Write V current I CC CC2 Output low voltage V OL2 V OL1 Capacitance (Ta = 25˚ MHz) Parameter Input capacitance (A0 to A2, SCL, WP) Cin* ...
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... Data out hold time Write cycle time Notes: 1. This parameter is sampled and not 100% tested the time from a stop condition to the end of internally controlled write cycle. WC HN58X24128FPIAG/HN58X24256FPIAG = 1 Symbol Min Typ f — — SCL t 1200 — ...
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... HN58X24128FPIAG/HN58X24256FPIAG Timing Waveforms Bus Timing t F SCL t SU.STA t HD.STA SDA (in SDA (out) Write Cycle Timing SCL D0 in SDA Write data (Address (n)) 6 1/f SCL t t LOW HIGH t HD.DAT t SU.DAT t DH Stop condition t WC ACK (Internally controlled SU.STO t BUF Start condition ...
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... SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed during SCL low period. Data Validity (SDA data change timing waveform) SCL SDA Note: High-to-low and low-to-high change of SDA should be done during SCL low periods. HN58X24128FPIAG/HN58X24256FPIAG Data change change , I and OL ...
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... HN58X24128FPIAG/HN58X24256FPIAG Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to V code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated ...
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... After the internally-timed write cycle which is specified as t timing) Start Condition and Stop Condition SCL SDA (in) Start condition HN58X24128FPIAG/HN58X24256FPIAG , the device enters a standby mode. (See write cycle WC Stop condition 9 ...
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... HN58X24128FPIAG/HN58X24256FPIAG Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words ...
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... A0 to A2. Device Address Word Device address word (8-bit) Device code (fixed) 128k, 256k 1 0 Note: 1. R/W=“1” is read and R/W = “0” is write. HN58X24128FPIAG/HN58X24256FPIAG Device address code R/W code R/W 1 ...
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... HN58X24128FPIAG/HN58X24256FPIAG Write Operations Byte Write: A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 128kbit and 256kbit EEPROMs receive 2 sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment " ...
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... Page Write Operation Device 1st Memory address address (n) 128k 256k ACK Start R/W Notes: 1. Don't care bits for 128k and 256k. 2. Don't care bit for 128k. HN58X24128FPIAG/HN58X24256FPIAG 2nd Memory address (n) Write data (n) ACK ACK Write data (n+m) ACK ACK Stop 13 ...
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... HN58X24128FPIAG/HN58X24256FPIAG Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM internally-timed write cycle or not. This features is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during a internally-timed write cycle. Acknowledge polling will operate R/W code = “ ...
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... The current address is valid while power is on. The current address after power on will be indefinite. The random read operation described below is necessary to define the memory address. Current Address Read Operation 128k to 256k Start HN58X24128FPIAG/HN58X24256FPIAG Device address Read data (n+ ...
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... HN58X24128FPIAG/HN58X24256FPIAG Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 2 8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition ...
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... The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition. Sequential Read Operation Device address 128k 256k Start R/W HN58X24128FPIAG/HN58X24256FPIAG Read data (n) Read data (n+1) Read data (n+2) ACK ACK Read data (n+m) ACK ACK No ACK Stop 17 ...
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... HN58X24128FPIAG/HN58X24256FPIAG Notes Data Protection at V On/Off CC When V is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) CC may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM have a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly ...
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... Package Dimensions HN58X24128FPIAG/HN58X24256FPIAG (FP-8DB) 5.15 Max 8 1 1.27 +0.063 *0.42 –0.064 0.40 0.06 *Dimension including the plating thickness Base material dimension HN58X24128FPIAG/HN58X24256FPIAG 4. 6.02 0.69 Max 0.60 0.10 0.25 M Hitachi Code JEDEC EIAJ Mass (reference value) Unit: mm 0.18 1.06 0 – 0.289 – 0.194 FP-8DB — — 0. ...
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... HN58X24128FPIAG/HN58X24256FPIAG Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...