A29L400A AMICC [AMIC Technology], A29L400A Datasheet - Page 15

• Manufacturer Part Number: A29L400A
• Description: 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
PD = Data to be programmed at location PA. Data latches on the rising edge of
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17 - A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Data bits I/O
5. Address bits A17 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
13. The Erase Resume command is valid only during the Erase Suspend mode.
PRELIMINARY
Program
Unlock Bypass
Unlock Bypass Program (Note 10) 2
Unlock Bypass Reset (Note 11)
Chip Erase
Sector Erase
Erase Suspend (Note 12)
Erase Resume (Note 13)
Read (Note 6)
Reset (Note 7)
(while the device is providing status data).
Continuation ID
Sector Protect Verify
(Note 9)
Device ID,
Top Boot Block
Device ID,
Bottom Boot Block
Manufacturer ID
whichever happens later.
Command
Sequence
(Note 1)
15
~I/O
(July, 2005, Version 0.0)
8
are don’t care for unlock and command cycles.
Word
Byte
Word
Byte
Word
Word
Word
Word
Word
Word
Word
Byte
Byte
Byte
Byte
Byte
Byte
Byte
4
4
4
4
4
4
3
6
6
1
1
1
1
2
Addr Data
Table 5. A29L400A Command Definitions
AAA
XXX
XXX
XXX
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
555
AAA
555
AAA
555
AAA
RA
XXX
XXX
First
AA
AA
AA
RD
AA
AA
AA
AA
A0
90
AA
B0
30
F0
AA
Addr
2AA
555
2AA
555
2AA
555
2AA
555
2AA
2AA
555
2AA
555
2AA
555
2AA
555
XXX
555
PA
Second
14
Data
55
55
55
55
55
55
55
PD
55
00
55
Bus Cycles (Notes 2 - 5)
AAA
Addr Data Addr
AAA
AAA
AAA
AAA
AAA
AAA 20
AAA
AAA
555
555
555
555
555
555
555
555
555
Third
WE
90
90
A0
80
80
90
90
90
or
CE
X00
(SA)
(SA)
X01
X02
PA
X03
X06
X04
555
AAA
555
AAA
X02
X01 B3B5
X02
Fourth
pulse, whichever happens first.
XX00
XX01
B334
AMIC Technology, Corp.
Data Addr Data
PD
AA
AA
34
00
01
37
B5
7F
A29L400A Series
2AA
555
2AA
555
Fifth
55
55
WE
Addr Data
or
SA
555
AAA
5
Sixth
CE
goes high
10
30
pulse,