AT83C24 ATMEL Corporation, AT83C24 Datasheet
AT83C24
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AT83C24 Summary of contents
Page 1
... The AT83C24 is a smart card reader interface IC for smart card reader/writer applica- tions such as EFT/POS terminals and set top boxes. It enables the management of any type of smart card from any kind of host AT83C24 can be connected in parallel using the programmable TWI address. ...
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... DVCC EVCC RESET PRES/ INT A2/CK, A1/RST, A0/3V, CMDVCC SCL SDA CLK I/O, C4, C8 AT83C24 2 TWI: Two-wire Interface POR: Power On Reset PFD: Power Fail Detect ART: Automatic Reset Transition ATR: Answer To Reset MSB: Most Significant Bit LSB: Least Significant bit SCIB: Smart Card Interface Bus ...
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... Remark: during power up and before registers configuration, the PRES/INT signal must be ignored. Microcontroller Interface Function: • Power-on reset • A low level on this pin keeps the AT83C24 under reset even if applied on power-on. It also resets the AT83C24 if applied when the AT83C24 is running (see Power I/O monitoring §). 3 kV open- • ...
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... CLK EVCC CIO CVCC CC4 CVCC CC8 CVCC CPRES VCC CCLK CVCC CRST CVCC CMDVCC EVCC VCC LI AT83C24 4 ESD Pad Limits Type Description I Microcontroller Interface Function open- TWI serial data drain I Microcontroller Interface Function open- TWI serial clock drain Microcontroller Interface Function Copy of CIO pin and high level reference for EVCC ...
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... DC/DC Ground 8 kV+ GND CVSS is used to sink high shunt currents from the external coil. GND Ground Note: ESD Test conditions: 3 positive and 3 negative pulses on each pin versus GND. Pulses generated according to Mil/STD 883 Class3. Recommended capacitors soldered on CVCC and VCC pins. AT83C24 5 ...
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... STOP. Write commands to the AT83C24 have the structure: ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S) Read commands to the AT83C24 have the structure: ADDRESS BYTE + DATA BYTE(S) The ADDRESS BYTE is sampled on A2/CK, A1/RST, A0/3V after each reset (hard/soft/general call) but A2/CK, A1/RST, A0/3V can be used for transparent mode after the reset ...
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... If A2/CK to A0/3V are tied to the host microcontroller and their reset values are unknown, a general call on the TWI bus allows to reset all the AT83C24 devices and set their address after A2/CK to A0/3V are fixed. Figure 2. Address Byte ...
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... Write Commands AT83C24 8 The write commands are: 1. Reset: Initializes all the logic and the TWI interface as after a power-up or power-fail reset smart card is active when RESET falls, a deactivation sequence is performed. This is a one-byte command. 2. Write Config: Configures the device according to the last six bits in the CONFIG0 register and to the following four bytes in CONFIG1, CONFIG2, CONFIG3 then CONFIG4 regis- ters ...
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... If IT_SEL=0, a read command of STATUS register and of CONFIG0 register will release PRES/INT pin to high level. Several AT83C24 devices can share the same interrupt and the microcontroller can identify the interrupt sources by polling the status of the AT83C24 devices using TWI commands. AT83C24 Byte Value ...
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... VCC Card Contact Presence PRES/INT External Pull-down VSS AT83C24 10 • If IT_SEL= 1 (mandatory for NDS applications and for software compatibility with existing devices) the PRES/INT output is High to indicate a card is present and none of the following event has occured: – over-current detection on CVCC – ...
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... Due to the minimum transfer delay allowed for NDS applications, the CLK minimum fre- quency is 18MHz. The clock controller generates two clocks (as shown in Figure 6 and Figure 7 clock for the CCLK: Four different sources can be used: CLK pin, DCCLK sig- nal, CARDCK bit or A2/CK pin (in transparent mode clock for DC/DC converter. AT83C24 CVCC 0 CIO 1 CVCC ...
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... CRST Controller AT83C24 12 Figure 6. Clock Block Diagram with Software Activation (see page 14) CLK DCK[2:0] CKS[2:0] A2/CK Figure 7. Clock Block Diagram with Hardware Activation (see page 14) CLK DCK[2:0] CKS[2:0] A2/CK CMDVCC A1/RST CRST_SEL bit The CRST output pin is driven by the A1/RST pin signal pin or by the CARDRST bit value ...
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... Figure 8. CRST Block Diagram with soft activation CARDRST bit tb delay see Fig 12 Figure 9. CRST Block Diagram with Hardware Activation (CMDVCC pin used) CARDRST bit A1/RST CMDVCC CRST_SEL bit = 1 CMDVCC AT83C24 ART bit 1 CRST_SEL bit = ART bit ...
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... Activation Sequence Hardware Activation (DC/DC started with CMDVCC) AT83C24 14 Initial conditions: CARDDET bit must be configured in accordance to the smart card connector polarity. IT_SEL bit, CRST_SEL bit (see CONFIG4 register) must be set and CARDRST bit (see INTERFACE register) must be cleared. A smart card must be detected to enable to start the DC/DC (CVCC 5V) ...
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... ATR. If the ATR arrives after the rising edge on CRST pin and before the card clock counter overflows (65535 clock cycles), the activation sequence completes. The Capture[1-0] register contains the value of the counter at the arrival of the ATR (tc time on Figure 11). AT83C24 15 ...
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... Software Activation (DC/DC Started by Writing in VCARD[1:0] bits) and ART bit = 0 AT83C24 16 Figure 11. Software activation with ART bit = 1 CARDRST bit set CVCC 3 1 CRST CCLK CIO ta 2 ISO 7816 constraints 200 card clock cycles 400 card clock cycles< 400 card clock cycles< < = 40000 card clock cycles Note: Timer[1-0] reset value is 400 ...
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... CKSTOP and IODIS are set (those bits are further explained in the registers description) Note: The user should check the AT83C24 status and possibly resume the activation sequence if one TWI transfer is not acknowledged during the activation sequence. The card automatic deactivation is triggered when one the following condition occurs: • ...
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... Td. If the microcontroller outputs ISO 7816 signals, a transparent mode allows to connect RST/CLK and I/O/C4/C8 signals after an electrical level control. The AT83C24 level shifters adapt the card signals to the smart card voltage selection. The CRST and CCLK microcontroller signals can be respectively connected to the A1/RST and A2/CK pins ...
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... First select the Low-power mode by setting the LP bit – The activation of the SHUTDOWN bit can then be done. The AT83C24 exits Power-down if a software/hardware reset is done or if SHUTDOWN bit is cleared. The AT83C24 is then active immediately. Either a hardware reset or a TWI command clearing the SHUTDOWN bit can cause an exit from Power-down ...
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... If EVCC and VCC have the same value, then they should be connected: The AT83C24 integrates an internal 3V regulator to feed its logic from the VCC sup- ply. The bit powermon allows the user to select if the internal PFD monitors VCC or the internal regulated 3V. If the PFD monitors VCC (POWERMON bit=0), a deacti- vation is performed if VCC falls below VPFDP (see VPFDP value in the datasheet) ...
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... VCARD[1:0] writing to 1.8V, 3V, 5V starts the DC/ card is detected. VCARD[1:0] writing to 0 stops the DC/DC. No card deactivation is performed when the voltage is changed between 1.8V 5V. The microcontroller should deactivate the card before changing the voltage. The reset value is 00 INSERT ICARDERR VCARDERR AT83C24 1 0 VCARD1 VCARD0 21 ...
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... When CDS[2- and IT_SEL = 0, PRES/INT = 1 when no card is present and PRES/INT = 0 when a card is inserted even if CLK is STOPPED. This can be used to wake up the external microcontroller and restart CLK when a card is inserted in the AT83C24. If CDS[2- IT_SEL = 1 and CLK is stopped, a card insertion or extraction has no effect on PRES/INT pin. 4 ...
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... The user can’t directly select A2 or A2/2 after a reset or when switching from CKS = ( CKS = (4, 5). To select A2, the user should select A2/2 first and after A2. To select A2/2, the user should select A2 first and after A2/ DCK0 X CKS2 CKS1 AT83C24 1 0 CKS0 23 ...
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... X VEXT0 if EVCC is supplied from the external EVCC pin, the user can switch off the internal EVCC regulator to decrease the consumption. If EVCC is switched off, and no external EVCC is supplied, the AT83C24 is inactive until a hardware reset is done. The reset value is 100. CI overflow adjust CC This bit controls the DC/DC sensitivity to any overflow current ...
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... Clear this bit to deactivate the internal pull-up. PRES/INT is an open drain output with a programmable internal pull up. The reset value is 0. Power monitor Set this bit to monitor any glitch on the Digital Supply Voltage (DVCC) of the AT83C24. 2 POWERMON Clear this bit to monitor any glitch on VCC. ...
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... Set this bit to drive the CIO, CC4, CC8 pins according to CARDIO, CARDC4, CARDC8 respectively and to put I/O, C4 Hi-Z. This can be used to have the I/O, and C4 and C8 pins of the host communicating with another AT83C24 interface, while CIO, CC4 and CC8 are driven by software (or if the card is in standby or 6 IODIS power-down modes) ...
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... The reset value is 0. Table 13. TIMER 1 (Timer MSB Bit 15 Bit 14 Bit 13 Bit Bit Number Mnemonic Description Bits Timer MSB (bits Reset value = 0x00000001 VCARDOK X VCARD_INT Bit 12 Bit 11 Bit 10 AT83C24 1 0 CRST CIO 1 0 Bit 9 Bit 8 27 ...
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... AT83C24 28 Table 14. TIMER 0 (Timer LSB Bit 7 Bit 6 Bit 5 Bit Bit Number Mnemonic Description bits Timer LSB (bits 7to 0) Reset value = 0x10010000 Table 15. CAPTURE 1 (Capture MSB bit 15 bit 14 bit 13 Bit Bit Number Mnemonic Description bits See “software activation with ART = 1”, page 15. ...
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... EVCC connected to host power supply: from 1.6V to 5. CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24 CLASS B card supplied with CVCC = 2.8V to 3.2V CLASS C card supplied with CVCC = 1.68V to 1.92V Min 2.4 2.25 ...
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... PRES/INT weak pull-up output current PRES/INT EVCC EVCC pin not connected to a power supply EVCC EVCC pin connected to a power supply CLK Clock signal for AT83C24 CLK Clock signal for AT83C24NDS Table 19. Host Interface (SCL, SDA, RESET) Symbol Parameter V Input Low-voltage ...
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... AT83C24 Unit Test Conditions 0 < Icard < 60mA C =10µF L for AT83C24 mV 0 < Icard < 65mA C = 3.3µF L for AT83C24NDS Max. charge 40 nA.s V Max. duration 400 ns Max. Icard variation 200 mA V AT83C24 V AT83C24NDS > V Icard = 0, VCC PFDP C = 3.3 F Icard = 0 ...
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... Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction. Table 23. Smart Card Clock (CCLK pin) Symbol Parameter V Output Low-voltage OL V Output High Voltage OH I Short Circuit Current Rise and Fall time R F AT83C24 32 Min Typ Max 140 250 110 250 130 250 100 250 (100kHz-100MHz), Min Typ Max ...
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... CVCC CVCC -20 +20 0.45 0 0.3 0.3 0.75 x CVCC CVCC 0.9 x CVCC CVCC -15 +15 -0.25 0.6 -0.25 0.4 -0.25 0.4 CVCC-0.5 CVCC+0.25 0.1 AT83C24 Unit Test Conditions CLASS A CCLK from 0.5 to 4.2V V/ns CLASS B CCLK from 0.5 to 0.85 x CVCC V CLASS A&B&C CVCC = CLASS A V CVCC = CLASS B CLASS C MHz C = 30pF, CLK=48MHz L Unit Test Conditions 500 µA IL µ ...
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... Table 26. Card Presence Symbol Parameter R CPRES weak pull-up output current CPRES Table 27. TWI (SDA, SCL pins) Symbol Parameter t Data set-up time SU;DAT t Data hold time HD;DAT t Fall time on SDA signal fDA AT83C24 34 Min Typ Max 0.12 x CVCC 0 0.4 0 0.2 0.9*CVCC CVCC -15 +15 0.1 0.50V -0.25 0.30V ...
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... Typical Application Figure 1. Typical Standard Mode Application Diagram for 3 AT83C24 ( AT83C24 if needed) EVCC Host MICROCONTROLLER XTAL1 XTAL2 MHz VSS VSS Note: 1. The external resistor on I/O can be removed if the host pin has an internal resistor VCC See note for I/O pull up SDA, ...
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... Typical NDS Application Figure 2. Typical NDS Standard Mode Application Diagram for 1 AT83C24NDS. EVCC Host MICROCONTROLLER XTAL1 XTAL2 18.432 or 27MHz VSS VSS AT83C24 36 See note VCC See note1 for I/O pull up SDA, Reset SCL pullup pullups TWI RST INT0 Px.y Px.y Px.y Px.y Note: 1. The external resistor on I/O can be removed if the host pin has an internal resistor. ...
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... AT83C24-PRTIM AT83C24-PRRIM AT83C24-TISIL AT83C24-TIRIL AT83C24-TISIM AT83C24-TIRIM AT83C24NDS-PRTIL AT83C24NDS-PRRIL AT83C24NDS-PRTIM AT83C24NDS-PRRIM AT83C24NDS-TISIL AT83C24NDS-TIRIL AT83C24NDS-TISIM AT83C24NDS-TIRIM LEAD FREE/ HALOGEN FREE: AT83C24-PRTUL AT83C24-PRRUL AT83C24-PRTUM AT83C24-PRRUM AT83C24-TISUL AT83C24-TIRUL AT83C24-TISUM AT83C24-TIRUM AT83C24NDS-PRTUL AT83C24NDS-PRRUL AT83C24NDS-PRTUM 4234E–SCR–09/04 Supply Voltage Temperature Range ( 5.5V Industrial ( 5.5V Industrial (2) 4.00V to 5.5V ...
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... Part Number AT83C24NDS-PRRUM AT83C24NDS-TISUL AT83C24NDS-TIRUL AT83C24NDS-TISUM AT83C24NDS-TIRUM Note: 1. Enhanced AC/DC parameters, see first page for differences between AT83C24 and AT83C24NDS. 2. Refer to index mark for proper placement. AT83C24 38 Supply Voltage Temperature Range (1)(2) 4.00V to 5.5V Industrial ( 5.5V Industrial ( 5.5V Industrial (1) 4.00V to 5.5V Industrial (1) 4.00V to 5.5V Industrial Package ...
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... Package Drawings QFN28 4234E–SCR–09/04 AT83C24 39 ...
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SO28 ...
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... Software workaround for A2 or A2/2 selection in CKS register. 3. Max speed on IO/CIO transfer 4. New conditions for hardware activation (see IT_SEL). 5. SO28 drawing package (error with SO32). 6. Adjusted electrical parameters for NDS compliance, pages 28, 29, 30. 1. QFN28 new package drawing. 2. Clock input parameters for AT83C24 and AT83C24NDS. AT83C24 41 ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...