LT1166 Linear Technology, LT1166 Datasheet - Page 7

• Manufacturer Part Number: LT1166
• Description: Power Output Stage Automatic Bias System
• Manufacturer: Linear Technology

APPLICATIONS
how tapping the sense resistors gives twice the limit
current or one half the limit current.
Foldback current limit can be added to the normal or
“square” current limit by including two resistors (30k
typical) from the power supplies to the I
in Figure 5. With square current limit the maximum output
current is independent of the voltage across the power
Figure 5. Unity Gain Buffer Amp with Foldback Current Limit
V
IN
R
+
IN
5.1k
330pF
Figure 4. Tapping Current Limit Resistors
2
330pF
2
V
IN
V
IN
V
LT1166
BOTTOM
V
V
LT1166
TOP
BOTTOM
U
V
1
4
TOP
SENSE
SENSE
1
4
SENSE
SENSE
20mA
20mA
I
I
V
LIM
LIM
OUT
INFORMATION
I
I
V
100
LIM
LIM
OUT
U
+
+
–
–
100
+
+
–
–
8
7
3
6
5
8
7
3
6
5
30k
30k
W
1 F
1 F
0.5
0.5
1
1
1k
1k
LIM
V +
V –
IRFR024
IRFR9024
pins as shown
1166 • F04
10
10
(2)(I
(1/2)(I
15V
–15V
V
mA
OUT
U
LIM
1166 • F05
LIM
)
)
V
OUT
Driving the Shunt Regulator
It is possible to current drive the shunt regulator directly
without driving the input transconductance stage. This
has the advantage of higher speed and eliminates the need
to compensate the g
LT1166 can be placed inside a feedback loop and
driven through the biasing current sources. The input
transconductance stage remains biased but has no effect
on circuit operation. The R
late the op amp supply current with input signal. This op
amp functions as a V-to-I with the supply leads acting as
current source outputs. The load resistor and the positive
input of the op amp are connected to the output of the
LT1166 for feedback to set A
eliminates output V
I
1/R
gain in the op amp before the phase of the MOSFETs
degenerate the stability of the loop.
devices. Foldback limit simply makes the output current
dependent on output voltage. This scheme puts dissipa-
tion limits on the output devices. The larger the voltage
across the power device, the lower the available output
current. This is represented in Figure 6, Output Voltage vs
Output Current for the circuit of Figure 5.
BOTTOM
F
C
F
. The zero frequency is selected to give a –1V/V
, and it also forms a pole at DC and a zero at
Figure 6. Output Current vs Output Voltage
–120
–160
–200
–40
–80
200
160
120
80
40
0
–10
–8
OS
–6
m
due to mismatch between I
OUTPUT VOLTAGE (V)
–4
SQUARE I
FOLDBACK I
FOLDBACK I
SQUARE I
stage. With Pin 2 floating, the
–2
L
in Figure 7 is used to modu-
0
V
LIM
LIM
= 1V/V. The capacitor C
LIM
LIM
+
–
2
–
+
4
6
LT1166 • F06
8
10
LT1166
TOP
and
7
F