74LCX126 Fairchild Semiconductor, 74LCX126 Datasheet
74LCX126
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74LCX126 Summary of contents
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... Each output is disabled when the associated output-enable (OE) input is LOW. The inputs tolerate voltages allowing the interface of 5V systems to 3V systems. The 74LCX126 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintaining CMOS low power dissipation. Ordering Code: ...
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Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...
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DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current CC I Increase in I per Input CC CC Note 5: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t PLH t Output Enable Time ...
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AC Loading and Waveforms (C t PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay, Pulse Width and t rec 3-STATE Output High Enable and Disable TImes for Logic (Input Pulse Characteristics 1MHz, t ...
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Schematic Diagram Generic for LCX Family 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow www.fairchildsemi.com Package Number M14A 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...