TC820 TelCom Semiconductor, TC820 Datasheet - Page 9

• Manufacturer Part Number: TC820
• Description: 3-3/4 DIGIT A/D CONVERTER WITH FREQUENCY COUNTER AND LOGIC PROBE
• Manufacturer: TelCom Semiconductor

3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit of
the dual-slope technique is noise immunity. Noise spikes
are integrated or averaged to zero during the integration
periods, making integrating ADCs immune to the large
conversion errors that plague successive approximation
converters in high-noise environments. Interfering signals,
with frequency components at multiples of the averaging
(integrating) period, will be attenuated (Figure 3). Integrating
ADCs commonly operate with the signal integration period
set to a multiple of the 50/60Hz power line period.
Analog Section
slope phases discussed above, the TC820 design incorpo-
rates a "zero integrator output" phase and an "auto-zero"
phase. These additional phases ensure that the integrator
starts at 0V (even after a severe overrange conversion), and
that all offset voltage errors (buffer amplifier, integrator and
where: V
For a constant t
Accuracy in a dual-slope converter is unrelated to the
In addition to the basic integrate and deintegrate dual-
Figure 3. Normal-Mode Rejection of Dual-Slope Converter
V
TELCOM SEMICONDUCTOR, INC.
IN
R
30
20
10
INT
= V
0.1/T
t
t
0
INT
DEINT
REF
1
T = MEASUREMENT
C
REF
INT
PERIOD
= Reference voltage
= Integration time
= Deintegration time
INT
t
:
DEINT
t
0
t
INT
INT
INPUT FREQUENCY
V
IN
(t) dt =
1/T
V
R
REF
INT
t
C
DEINT
INT
10/T
comparator) are removed from the conversion. A true digital
zero reading is assured without any external adjustments.
Zero Integrator Output Phase
before the system zero phase is entered, ensuring that the
true system offset voltages will be compensated for even
after an overrange conversion. The duration of this phase is
500 counts plus the unused deintegrate counts.
Auto-Zero Phase
is disconnected from the measurement circuit by opening
internal analog switches, and the internal nodes are shorted
to Analog Common (0V
tion. Additional analog switches close a feedback loop
around the integrator and comparator to permit comparator
offset voltage error compensation. A voltage established on
C
during the measurement cycle. The auto-zero phase re-
sidual is typically 10 V to 15 V. The auto-zero duration is
1500 counts.
Signal Integration Phase
loop is opened and the internal differential inputs connect to
V
for a fixed time period, which is 2000 counts (4000 clock
periods). The externally-set clock frequency is divided by
two before clocking the internal counters. The integration
time period is:
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, as in battery-powered applications,
V
phase. The sign bit is a "true polarity" indication in that
signals less than 1 LSB are correctly determined. This
allows precision null detection that is limited only by device
noise and auto-zero residual offsets.
IN
IN
AZ
+
–
A complete conversion consists of four distinct phases:
(1) Zero Integrator Output
(2) Auto-Zero
(3) Signal Integrate
(4) Reference Deintegrate
This phase guarantees that the integrator output is at 0V
During the auto-zero phase, the differential input signal
Upon completion of the auto-zero phase, the auto-zero
t
The differential input voltage must be within the device's
Polarity is determined at the end of signal integration
then compensates for internal device offset voltages
and V
INT
should be tied to analog common.
=
IN
4000
f
–
OSC
. The differential input signal is then integrated
REF
) to establish a zero input condi-
TC820
3-157
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