P89C668 Philips Semiconductors, P89C668 Datasheet
P89C668
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P89C668 Summary of contents
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... P89C668 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM Preliminary data Supersedes data of 2001 Jul 19 IC28 Data Handbook hilips Semiconductors INTEGRATED CIRCUITS 2001 Jul 27 ...
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... The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P89C668 makes it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. ...
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... LATCH LATCH STACK POINTER TMP2 TMP1 ALU SFRs TIMERS PSW P.C.A. PORT 1 PORT LATCH PORT 1 PORT 3 DRIVERS DRIVERS SCL SDA P1.0–P1.7 P3.0–P3.7 3 Preliminary data P89C668 FLASH 8 PROGRAM ADDRESS REGISTER BUFFER PC INCRE- MENTER 8 16 PROGRAM COUNTER DPTR’S MULTIPLE LATCH su01089 ...
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... Pin Function 31 P2.7/A15 32 PSEN 33 ALE 34 NIC P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0 SU01091 4 Preliminary data P89C668 LQFP Pin Function Pin Function P0.6/AD6 SS 17 NIC* 32 P0.5/AD5 18 P2.0/A8 33 P0.4/AD4 34 P0.3/AD3 19 P2.1/A9 35 P0.2/AD2 20 P2.2/A10 36 P0.1/AD1 21 P2 ...
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... As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics Port 3 also serves the special features of the P89C668, as listed below: IL RxD (P3.0): Serial input port TxD (P3 ...
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... The value on the EA pin is latched when RST is released and any subsequent changes have no effect. Since the P89C668 has 64k internal memory, the P89C668 will execute only from internal memory when EA is held high. This pin also receives the programming supply voltage (V PP Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits ...
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... A4 A3 AD15 AD14 AD13 AD12 AD11 T1/ T0/ INT1 CEX4 CEX3 SMOD1 SMOD0 – POF GF1 7 Preliminary data P89C668 RESET LSB VALUE 00H – EXTRAM AO xxxxxx10B 0 – DPS xxxxxxx0B 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB ...
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... RST must come up at the same time for a proper start-up. CC Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above V The value on the EA pin is latched when RST is deasserted and has no further effect. 8 Preliminary data P89C668 RESET LSB VALUE ...
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... POWER OFF FLAG The Power Off Flag (POF) is set by on-chip circuitry when the V level on the P89C668 rises from The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power- warm start after powerdown. The V ...
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... MHz/15 MHz the maximum I OSC 2001 Jul 27 Note that in both the P89C668 and the 8XC552 the I alternate functions to port pins P1.6 and P1.7. Because of this, P1.6 and P1.7 on these parts do not have a pull-up structure as found on the 80C51. Therefore P1.6 and P1.7 have open drain outputs on the P89C668. ...
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... TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation. RCLK TCLK EXEN2 TR2 11 Preliminary data P89C668 (LSB) C/T2 CP/RL2 SU01209 ...
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... Baud rate generator 0 (off) TL2 TH2 (8-bits) (8-bits) Control TR2 Capture RCAP2L RCAP2H Control Figure 2. Timer 2 in Capture Mode — — — — Preliminary data P89C668 MODE TF2 Timer 2 Interrupt EXF2 SU01210 Reset Value = XXXX XX00B T2OE DCEN 1 0 SU00729 ...
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... CONTROL (DOWN COUNTING RELOAD VALUE) FFH FFH OVERFLOW TL2 TH2 CONTROL RCAP2L RCAP2H (UP COUNTING RELOAD VALUE) Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) 13 Preliminary data P89C668 TF2 TIMER 2 INTERRUPT EXF2 SU01211 TOGGLE EXF2 TF2 INTERRUPT COUNT DIRECTION DOWN T2EX PIN ...
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... TH2 and TL2 baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be 14 Preliminary data P89C668 Timer 1 Overflow 2 “0” “1” ...
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... Also see Table 7 for set-up of Timer counter. T2CON INTERNAL CONTROL EXTERNAL CONTROL (Note 1) 00H 01H 34H 24H 14H TMOD INTERNAL CONTROL EXTERNAL CONTROL (Note 1) 02H 03H 15 Preliminary data P89C668 f OSC Baud Rate (Note 2) 08H 09H 36H 26H 16H (Note 2) 0AH 0BH ...
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... This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. 16 Preliminary data P89C668 ...
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... SM2 REN TB8 RB8 Description Baud Rate** shift register f /6 OSC 8-bit UART variable 9-bit UART f / /16 OSC OSC 9-bit UART variable Figure 7. S0CON: Serial Port Control Register 17 Preliminary data P89C668 Reset Value = 0000 0000B SU01457 ...
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... POF LVF GF0 Figure 8. UART Framing Error Detection SM0 SM1 SM2 REN COMPARATOR 18 Preliminary data P89C668 D7 D8 ONLY IN STOP MODE 2, 3 BIT S0CON TI RI (98H) PCON GF1 IDL (87H) SU01458 D7 D8 S0CON TB8 RB8 TI RI ...
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... Flash microcontroller family 64KB ISP Flash with 8KB RAM Interrupt Priority Structure The P89C668 has an 8 source four-level interrupt structure (see Table 8). There are 4 SFRs associated with the four-level interrupt. They are the IE, IEN1, IP, and IPH. (See Figures 10, 11, 12, and 13.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible ...
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... Figure 11. IP Registers PS1H PS0H PT1H PX1H 2 C) interrupt priority bit high. Figure 12. IPH Registers — — — — Figure 13. IEN1 Registers 20 Preliminary data P89C668 1 0 PT0 PX0 SU01461 1 0 PT0H PX0H SU01462 1 0 — ET2 SU01095 ...
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... MOVX @ DPTR , A 1 JMP @ A + DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details. 21 Preliminary data P89C668 DPTR1 DPTR0 DPH DPL (83H) (82H) EXTERNAL ...
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... Flash microcontroller family 64KB ISP Flash with 8KB RAM Programmable Counter Array (PCA) The Programmable Counter Array available on the and P89C668 is a special 16-bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator ...
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... CF CR –– CCF4 CCF3 Figure 16. PCA Timer/Counter CF CR –– CCF4 CCF3 CCAPMn.0 ECCFn Figure 17. PCA Interrupt System 23 Preliminary data P89C668 TO PCA MODULES OVERFLOW INTERRUPT CL CMOD CPS1 CPS0 ECF (C1H) CCON CCF2 CCF1 CCF0 (C0H) SU01096 CCON ...
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... External clock at ECI/P1.2 pin (max. rate = f Figure 18. CMOD: PCA Counter Mode Register – CCF4 CCF3 CCF2 Figure 19. CCON: PCA Counter Control Register 24 Preliminary data P89C668 Reset Value = 00XX X000B CPS0 ECF OSC SU01098 Reset Value = 00X0 0000B CCF1 CCF0 1 ...
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... CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode. 25 Preliminary data P89C668 Reset Value = X000 0000B PWMn ECCFn 1 0 ...
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... CCF4 CCF3 CCF2 CCAPnL (TO CCFn) MATCH CL ECOMn CAPPn CAPNn MATn TOGn Figure 23. PCA Compare Mode 26 Preliminary data P89C668 CCON CCF0 (0C0H) PCA INTERRUPT PCA TIMER/COUNTER CH CL CCAPnH CCAPnL CCAPMn ECCFn (C2H – C6H) SU01101 CCON CCF1 CCF0 (C0H) ...
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... ENABLE 8–BIT COMPARATOR CL >= CCAPnL CL OVERFLOW PCA TIMER/COUNTER CAPPn CAPNn MATn TOGn PWMn Figure 25. PCA PWM Mode 27 Preliminary data P89C668 CCON CCF1 CCF0 (C0H) PCA INTERRUPT TOGGLE CEXn CCAPMn, n: 0..4 PWMn ECCFn (C2H – C6H SU01103 0 CEXn 1 CCAPMn, n: 0..4 ECCFn (C2H – ...
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... Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 16 2 count of the PCA timer. 28 Preliminary data P89C668 CMOD CPS1 CPS0 ECF (C1H) RESET CCAPM4 ...
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... Main program goes here, but CALL WATCHDOG periodically. ; ;******************************************************************** ; WATCHDOG: CLR EA ; Hold off interrupts MOV CCAP4L, #00 ; Next compare value is within MOV CCAP4H 255 counts of the current PCA SETB EA ; timer value RET Figure 27. PCA Watchdog Timer Initialization Code 2001 Jul 27 29 Preliminary data P89C668 ...
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... Flash microcontroller family 64KB ISP Flash with 8KB RAM Expanded Data RAM Addressing The P89C668 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 7936 bytes expanded RAM (ERAM) ...
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... Figure 29. Internal and External Data Memory Address Space with EXTRAM = 0 HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR P89C668) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset ...
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... Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V 2001 Jul 27 RATING 0 to +70 or –40 to +85 –65 to +150 0 to +13.0 –0.5 to +6.5 15 1.5 32 Preliminary data P89C668 UNIT unless otherwise noted. SS ...
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... ALE and PSEN to momentarily fall below the Freq. CC FREQ. +1.0) clock mode. must be externally limited as follows the voltage specification specification input voltage below 1.5 V will be recognized as a logic 0 33 Preliminary data P89C668 LIMITS UNIT UNIT 1 MIN TYP MAX –0.5 0.2 V –0 – ...
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... CLCL 0 1.5t CLCL 2t –75 CLCL 0.5t CLCL 0.5t CLCL 3.5t –130 CLCL 0.5t CLCL CLCL 5t –133 CLCL t –30 CLCL 0 34 Preliminary data P89C668 MHz CLOCK MAX MIN MAX UNIT MHz 10 ns – – – CLCL – – 1.5t – ...
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... CLCL CLCL CLCL 300 ns will be filtered out. Maximum capacitance on bus-lines SDA and CLCL 35 Preliminary data P89C668 OUTPUT 4 > 4 > 4 > 4 – 6 < 0.3 s > – t CLCL RD 4 > > CLCL > ...
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... CLCL 4t –75 CLCL t –30 CLCL t –25 CLCL 7t –130 CLCL t –25 CLCL 17 17 12t CLCL 10t –133 CLCL 2t –80 CLCL 0 36 Preliminary data P89C668 MHz CLOCK MAX MIN MAX UNIT MHz – CLCL –60 ...
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... CLCL CLCL 300 ns will be filtered out. Maximum capacitance on bus-lines SDA and CLCL < 285 ns (16 MHz > f > 3.5 MHz) the I CLCL OSC 37 Preliminary data P89C668 OUTPUT 4 > 4 > 4 > 4 – 6 < 0.3 s > – t CLCL RD 4 > > ...
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... RHDX DATA IN t AVDV P2.0–P2.7 OR A8–A15 FROM DPF Figure 31. External Data Memory Read Cycle 38 Preliminary data P89C668 = Time for address valid to ALE low. =Time for ALE low to PSEN low. A0–A7 A8–A15 SU00006 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH ...
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... Figure 33. Shift Register Mode Timing –0.5 0.7V CC 0.2V –0 CHCX CHCL CLCX CLCH t CLCL Figure 34. External Clock Drive 39 Preliminary data P89C668 A0–A7 FROM PCL INSTR IN A0–A15 FROM PCH SU00026 SET TI VALID VALID VALID VALID SET RI SU00027 SU00009 ...
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... SU00717 89C668 MAXIMUM ACTIVE I CC TYPICAL ACTIVE I MAXIMUM IDLE Frequency at XTAL1 (MHz, 6 clock mode) Figure 37. I vs. FREQ CC 40 Preliminary data P89C668 V –0.1V TIMING OH REFERENCE POINTS V +0. 20mA SU00718 Figure 36. Float Waveform CC TYPICAL IDLE ...
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... V max for a logic ‘0’ Figure 39. AC Testing Input/Output +0.1V TIMING V REFERENCE POINTS –0. level occurs Figure 40. Float Waveform 41 Preliminary data P89C668 START condition t SU;STA 0 0 BUF t SU;STO 0 0 SU;DAT3 t SU;DAT2 ...
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... SU01111 Figure 44. I Test Condition, Power Down Mode CC All other pins are disconnected 5 through resistors of sufficiently high value such that the sink current into these pins does not CC 42 Preliminary data P89C668 RST 89C668 P1 ...
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... CAPABILITIES OF THE PHILIPS 89C51 FLASH-BASED MICROCONTROLLERS Flash organization The P89C668 contains 64 kbytes of Flash program memory. This memory is organized as 5 separate blocks. The first two blocks are 8 kbytes in size, filling the program memory space from address 0 through 3FFF hex. The final three blocks are 16 kbytes in size and occupy addresses from 4000 through FFFF hex ...
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... The P89C668 contains two special Flash registers: the BOOT VECTOR and the STATUS BYTE. At the falling edge of reset, the P89C668 examines the contents of the Status Byte. If the Status Byte is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code. ...
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... ASCII characters used to represent hexadecimal values and are summarized below: :NNAAAARRDD..DDCC<crlf> In the Intel Hex record, the “NN” represents the number of data bytes in the record. The P89C668 will accept (10H) data bytes. The “AAAA” string represents the address of the first byte in 2001 Jul 27 V ...
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... Example: :00000001FF 02 Specify Oscillator Frequency :01xxxx02ddcc Where: xxxx = required field, but value is a “don’t care” integer oscillator frequency rounded down to nearest MHz cc = checksum Example: :0100000210ED 2001 Jul 27 COMMAND/DATA FUNCTION (dd = 10h = 16, used for 16.0–16.9 MHz) 46 Preliminary data P89C668 ...
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... Example: :0500000440004FFF0069 2001 Jul 27 COMMAND/DATA FUNCTION 0k to 8k, 00H 8k to 16k, 20H erase block 4 erase boot vector and status byte (inhibit writing to Flash) (inhibit Flash verify) (disable eternal memory) program security bit 2 program boot vector display 4000–4FFF 47 Preliminary data P89C668 ...
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... Load of Baud Rate” function code hh = high byte of Timer low byte of Timer checksum Example: :02000006F50003 2001 Jul 27 COMMAND/DATA FUNCTION (P89C668 = 81H) read signature byte – device Preliminary data P89C668 (C2H) ...
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... ACC = status byte 2001 Jul 27 Using the Watchdog Timer (WDT) The P89C668 supports the use of the WDT in IAP. The user specifies that the WDT fed by setting the most significant bit of the function passed in R1 prior to calling PCM_MTP. The WDT function is only supported for Block Erase when using the Quick Block Erase ...
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... DPH = 00h DPL = 01h (status byte) Return Parameter ACC = value of byte read READ BOOT VECTOR Input Parameters osc freq (integer 07h R1 = 87h (WDT feed) DPH = 00h DPL = 02h (boot vector) Return Parameter ACC = value of byte read 2001 Jul 27 PARAMETER 50 Preliminary data P89C668 ...
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... The security feature protects against software piracy and prevents the contents of the Flash from being read. The Security Lock bits are located in Flash. The P89C668 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 11) ...
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... Philips Semiconductors 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM PLCC44: plastic leaded chip carrier; 44 leads 2001 Jul 27 52 Preliminary data P89C668 SOT187-2 ...
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... Philips Semiconductors 80C51 8-bit Flash microcontroller family 64KB ISP Flash with 8KB RAM LQFP44: plastic low profile quad flat package; 44 leads; body 1.4 mm 2001 Jul 27 53 Preliminary data P89C668 SOT389-1 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2001 Jul 27 Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Document order number: 54 Preliminary data P89C668 Date of release: 07-01 9397 750 08651 ...