W78E51B Winbond, W78E51B Datasheet
W78E51B
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W78E51B Summary of contents
Page 1
... GENERAL DESCRIPTION The W78E51B is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption. The instruction set for the W78E51B is fully compatible with the standard 8051. The W78E51B contains an 4K bytes MTP ROM (Multiple-Time Programmable ROM); a 128 bytes RAM ...
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... ALE 12 29 INT0, P3.2 PSEN 13 P2.7, A15 28 INT1, P3.3 14 T0, P3.4 27 P2.6, A14 15 T1, P3.5 26 P2.5, A13 16 WR, P3.6 25 P2.4, A12 17 24 P2.3, A11 RD, P3.7 18 XTAL2 23 P2.2, A10 XTAL1 19 22 P2. VSS 21 P2.0, A8 44-Pin QFP (W78E51BF P1.5 P0.4, AD4 39 P1.6 38 P0.5, AD5 37 P1.7 P0.6, AD6 RST 36 P0.7, AD7 RXD, P3.0 ...
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... Timer 1 External Input WR (P3.6) : External Data Memory Write Strobe RD (P3.7) : External Data Memory Read Strobe P4.0 P4.3 PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O port or external interrupt input sources ( INT2 / INT3 ). Preliminary W78E51B DESCRIPTIONS Publication Release Date: December 1998 - 3 - Revision A1 ...
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... XTAL1 FUNCTIONAL DESCRIPTION The W78E51B architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space ...
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... POLLING SEQUENCE WITHIN PRIORITY LEVEL 03H 0 (highest) 0BH 1 13H 2 1BH 3 23H 4 33H 5 3BH 6 (lowest) ; Output data "A" through P4.0 P4.3. ; Read P4 status to Accumulator. ; Set bit P4.0 ; Clear bit P4 Preliminary W78E51B IE2 IT2 ENABLE INTERRUPT REQUIRED TYPE SETTINGS EDGE/LEVEL IE.0 TCON.0 IE.1 - IE.2 TCON.2 IE.3 - IE.4 - XICON.2 XICON.0 XICON.6 XICON ...
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... ROM code space. The AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation circuitry, W78E51B allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the B7 bit of security register. Once B7 is set half of gain will be decreased ...
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... CLRW WIDL - Mnemonic: WDTC Address: 8FH PRESCALER SELECT 128 1 256 ENW EXTERNAL RESET PRESCALER CLRW - 7 - Preliminary W78E51B PS2 PS1 INTERNAL 14-BIT TIMER RESET CLEAR Publication Release Date: December 1998 Revision A1 0 PS0 ...
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... The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E51B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. ...
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... Program/Erase Inhibit Operation This operation allows parallel erasing or programming of multiple chips with different data. When P3. P3. except for the P3.6 and P3.7 pins, the individual chips may have common inputs. Preliminary W78E51B , erasing or programming of non-targeted chips is inhibited. So, IH Publication Release Date: December 1998 - 9 - Revision A1 ...
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... During the on-chip MTP-ROM operation mode, the MTP-ROM can be programmed and verified repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The protection of MTP ROM and those operations on it are described below. The W78E51B has several Special Setting Registers, including the Security Register and Company/Device ID Registers, which can not be accessed in normal mode ...
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... Default 1 for all security bits. Lock bit This bit is used to protect the customer's program code in the W78E51B. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the MTP ROM data and Special Setting Registers can not be accessed again. ...
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... Current P1, P2 Input Current (*2) RST Input Leakage Current P0, EA Output Low Voltage P1, P2, P3, P4 Output Low Voltage (*3) ALE, PSEN , P0 Output High Voltage P1, P2, P3, P4 Output High Voltage (*3) ALE, PSEN , P0 Preliminary W78E51B SYMBOL MIN -55 ...
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... Vs = 0.45V 4.5V IH2 4.5V IH3 4.5V SK2 0.45V 4.5V SR1 2. 4.5V SR2 2. Preliminary W78E51B SPECIFICATION MIN. MAX. 0 0.8 0 0.8 0 0.8 2 -100 -250 -8 -14 ), and actual parts will CP Publication Release Date: December 1998 ...
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... ALE Low to RD Low RD Low to Data Valid Data Hold from RD High Data Float from RD High RD Pulse Width Notes: 1. Data memory access time " " (due to buffer driving delay and wire loading nS. Preliminary W78E51B OP, CP SYMBOL MIN ...
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... OECTRL Setup Time OECTRL Hold Time OE Setup Time OE High to Output Float Data Valid from OE Note: Flash data can be accessed only in flash mode. The RST pin must pull in V the PSEN pin must pull in V status. IH Preliminary W78E51B SYMBOL MIN. TYP DAW ...
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... Data Read Cycle S4 S5 XTAL1 ALE PSEN PORT 2 A0-A7 PORT ALW T APL T PSW T AAS T PDA T T PDH, PDZ A0-A7 A0-A7 Code A0-A7 Data A8-A15 DATA T T DAR DDA T DDH, T DRD - 16 - Preliminary W78E51B Data A0- DDZ ...
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... PSEN PORT 2 PORT 0 A0-A7 WR Port Access Cycle XTAL1 ALE T PDS PORT INPUT SAMPLE A8-A15 DATA OUT T DAD T T DAW DWR PDH - 17 - Preliminary W78E51B DWD S1 T PDA DATA OUT Publication Release Date: December 1998 Revision A1 ...
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... (CE P3.3 IH (OECTRL P3 (OE (A7... A0 Vcp Vpp VPS Program Program Verify Address Stable T PWP OCS T OCH T OES Data In OUT T OEV - 18 - Preliminary W78E51B Read Verify Address Valid DFP Data Out ...
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... P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 P1.6 8 P1.7 W78E51B CRYSTAL 16 MHz 24 MHz 33 MHz 40 MHz Above table shows the reference values for crystal applications (full gain). Note: C1, C2, R components refer to Figure A. Preliminary W78E51B AD0 39 AD0 P0.0 38 AD1 AD1 P0.1 37 AD2 AD2 ...
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... INT0 P2.2 23 A10 P2.3 24 A11 INT1 25 P2.4 A12 T0 P2.5 26 A13 T1 P2.6 27 A14 28 P2.7 P1 P1.3 29 P1.4 PSEN 30 P1.5 ALE 11 P1.6 TXD 10 RXD P1.7 Figure Preliminary W78E51B ...
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... E Base Plane A 1 Seating Plane Preliminary W78E51B Dimension in inch Dimension in mm Symbol Min. Nom. Nom. Max. Min. A 0.210 0.010 0.254 0.150 0.155 0.160 3.81 3.937 2 B 0.016 0.018 0.022 0.406 ...
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... See Detail F Seating Plane Detail Detail Preliminary W78E51B Dimension in inch Dimension in mm Symbol Min. Nom. Max. Min. Nom. A --- --- --- --- --- A 0.002 0.01 0.02 0.25 0. 0.081 0.087 0.075 1.90 2. 0.01 0.014 0.25 0.018 0. ...
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... No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. Preliminary W78E51B Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U ...