AM79C873 Advanced Micro Devices, AM79C873 Datasheet
AM79C873
Available stocks
Related parts for AM79C873
AM79C873 Summary of contents
Page 1
... PRELIMINARY Am79C873 NetPHY™ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support DISTINCTIVE CHARACTERISTICS 100BASE-FX direct interface to industry standard electrical/optical transceivers 10/100BASE-TX physical-layer, single-chip transceiver Compliant with the IEEE 802.3u 100BASE-TX standard Compliant with the ANSI X3T12 TP-PMD 1995 standard Compliant with the IEEE 802 ...
Page 2
... Serial MLT-3 NRZI 25M CLK 125M CLK Code- Serial to NRZI to group Descrambler NRZ Parallel Alignment Digital Logic Carrier Collision Sense Detection Am79C873 LED1-4 LED Driver PECL Driver MLT-3 Driver Rise/Fall Time CTL MLT-3 to Adaptive NRZI EQ RX CRM PECL Receiver RX 10BASE-T ...
Page 3
... AGND 18 FXTD- 19 FXTD AGND 23 AGND 24 100TXO- 25 100TXO OSCI/ Am79C873/KC NetPHY-1 Am79C873 80 RX_EN RX_ER/RXD4 79 RX_DV 78 77 COL 76 CRS 75 RX_CLK DGND 73 72 RXD0 71 RXD1 70 RXD2 RXD3 DGND ...
Page 4
... NetPHY-1™ 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C873 Valid Combinations ...
Page 5
... Basic Integrated Multiport Repeater (bIMR) Am79C983 Integrated Multiport Repeater 2 (IMR2™) Am79C984A Enhanced Integrated Multiport Repeater (eIMR™) Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™) Am79C987 Hardware Implemented Management Information Base (HIMIB™ Description Am79C873 5 ...
Page 6
... Auto-Negotiation Link Partner Ability Register (ANLPAR) - Register Auto-Negotiation Expansion Register (ANER) - Register AMD Specified Configuration Register (DSCR) - Register AMD Specified Configuration and Status Register (DSCSR) - Register 17 10BASE-T Configuration/Status (10BTCSRSCR) - Register Am79C873 ...
Page 7
... Jab and Unjab Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10BASE-T Jab and Unjab Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MDIO Timing when OUTPUT by STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MDIO Timing when OUTPUT by NetPHY-1 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MII Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MAGNETICS SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CRYSTAL SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 NETPHY-1 MII EXAMPLE SCHEMATIC PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Am79C873 7 ...
Page 8
... Receive Error This pin is asserted high to indicate that an invalid sym- bol has been detected inside a received packet in 100 Mbps mode bypass mode (BP4B5B or BPALIGN modes), Input/Output RX_ER becomes RXD4, the fifth RXD data bit of the 5B symbols. Am79C873 1 Output/Z 1 Output/Z 1 Output/Z 1 ...
Page 9
... LED to indicate that 100 Mbps operation is selected. RX_LOCK Lock for Clock/Data Recovery PLL Output When this pin is high, it indicates that the receiver re- covery PLL logic has locked to the input data stream. Am79C873 Output Output Output Drain Output Drain Output Output ...
Page 10
... Transmit and receive data is ex- Manual select changed in nibbles on the TXD[3:0] and RXD[3:0] pins 100FX HDX respectively. Auto-Negotiation At power-up/reset, the value on this pin is latched into 10/100TX. HDX Register 18, bit 10. only Am79C873 Input Input Input Input Input ...
Page 11
... These pins are the digital supply pairs. Input AGND Analog Circuit Ground These pins are the analog circuit supply pairs. AVCC Analog Circuit Power Supply These pins are the analog circuit supply pairs. Am79C873 Input Input , 1% resistor between this pin and Input resistor connection. Input Input ...
Page 12
... RX_CLK period which RX_DV is asserted, RXD (3:0) are transferred from the PHY to the MAC reconciliation sublayer. RX_CLK (receive clock) output to the MAC reconcil- iation sublayer is a continuous clock that provides the timing reference for the transfer of the RX_DV, RXD, and RX_ER signals. Am79C873 22164A-3 pre- ...
Page 13
... NetPHY-1 device and the Reconciliation layer. 100BASE Transmit The 100BASE transmitter consists of the functional blocks shown in Figure 3. The 100BASE transmit sec- tion converts 4-bit synchronous data provided by the MII to a scrambled MLT-3 125 million symbols per sec- ond serial data stream. Am79C873 ESD IDLE T/R EFD 22164A-4 13 ...
Page 14
... Transmit Enable is asserted and the next transmit packet is detected. The NetPHY-1 device includes a Bypass 4B5B conver- sion option within the 100BASE-TX transmitter for sup- port of applications like 100 Mbps repeaters which do not require 4B5B conversion. Am79C873 LED1-4# LED Driver PECL FXTD ...
Page 15
... MLT-3 Converter 11001 The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two bi- nary data streams with alternately phased logic one events. Am79C873 is for RIOL will yield 15 ...
Page 16
... The selection of long cable lengths for a given implementation, requires sig- nificant compensation which will be over-kill in a situa- tion that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermedi- ate cable lengths requiring less compensation will Am79C873 MLT-3 22164A-6 ...
Page 17
... Auto-Negotiation also provides a parallel detection function for devices that do not support the Auto-Nego- tiation feature. During Parallel detection there is no ex- change of configuration information, instead, the receive signal is examined discovered that the signal matches a technology that the receiving device Am79C873 17 ...
Page 18
... The MDIO pin is bidirectional and may be shared devices PHY Address Register Address Turn Around Write PHY Address Register Address Turn Around Write Am79C873 D15 D14 Data Idle Read 22164A D15 D14 D1 D0 Data Idle 22164A-8 ...
Page 19
... Auto-Negotiation Expansion Register AMD Specified Configuration Register AMD Specified Configuration/Status Register 10BASE-T Configuration/Status Register Reserved For Future Use-Do Not Read/Write To These Registers <Access Type> Read only RW = Read/Write <Attribute (s)> Self clearing P = Value permanently set LL = Latching low LH = Latching high Am79C873 19 ...
Page 20
... When this bit is set the data path will be isolated from the MII interface. TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL and CRS will be 00000), placed in a high impedance state. The management interface is not RW effected by this bit. When the PHY Address is set to 00000 the isolate bit will be set upon power-up/reset. Am79C873 Description ...
Page 21
... Full Duplex mode. When Auto-Negotiation is enabled, this bit reflects the duplex selected by Auto-Negotiation. Collision Test: 1= Collision Test enabled Normal Operation When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN. Reserved Write as 0, ignore on read. Am79C873 Description 21 ...
Page 22
... Mbps or 100 Mbps operation). 0=Link not established. The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the Link Status bit to be cleared and remain cleared until it is read via the management interface. Am79C873 Description ...
Page 23
... Bits the OUI (00606E) are mapped to bits this register, respectively. Vendor Model Number: Six bits of the vendor model number mapped to bits (most significant bit to bit 9). Model Revision Number: Four bits of the vendor model revision number mapped to bits (most significant bit to bit 3). Am79C873 Description Description 23 ...
Page 24
... Full Duplex not supported. 10BASE-T Support 1=10BASE-T supported by the local device. 0=10BASE-T not supported. Protocol Selection Bits: These bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports IEEE 802.3 CSMA/CD. Am79C873 Description ...
Page 25
... Full Duplex supported by the link partner. 0=10BASE-T Full Duplex not supported by the link partner. 10BASE-T Support 1=10BASE-T Half Duplex supported by the link partner. 0=10BASE-T Half Duplex not supported by the link partner. Protocol Selection Bits: Link partners binary encoded protocol selector. Am79C873 Description 25 ...
Page 26
... NetPHY-1 device does not support this function, so this bit is always 0. New Page Received: A new link code word page received. This bit will be automatically cleared when the register (Register 6) is read by management. Link Partner Auto-Negotiation Able LP_AN_ABLE=1 indicates that the link partner supports Auto- Negotiation. Am79C873 Description ...
Page 27
... For applications requiring the CLK25M output, set this bit to 0. Force Good Link in 100 Mbps: 1=Normal 100 Mbps operation 0=Force 100 Mbps good link status. This bit is useful for diagnostic purposes. Reserved This bit must be written as 0. Am79C873 Description 27 ...
Page 28
... Sleep mode, write 0 to this bit position. The prior configuration will be retained when the sleep state is terminated, but the state machine will be reset. Remote Loopout Control When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing. Am79C873 Description ...
Page 29
... Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detect signal_link_ready Parallel detect signal_link_ready fail Auto-Negotiation completed successfully Am79C873 Description Description 29 ...
Page 30
... The value on the 10BTSER input pin is latched into this bit at power-up/ rese.t Serial mode not supported for 100 Mbps operation. Reserved Write as 0, ignore on read. Polarity Reversed When this bit is set indicates that the 10M cable polarity is reversed. This bit is set and cleared by 10BASE-T module automatically. Am79C873 Description ...
Page 31
... MII Register 0 Bit 11 set true) Conditions -400 100 0 2 Am79C873 ) Min Typical Max Unit 180 185 mA 120 mA 220 165 mA 115 mA 0.8 V 2.0 V -200 uA 100 uA 31 ...
Page 32
... Cycle Distortion 100TXO+/- Differential Output Peak-to- t T/T Peak Jitter 100TXO+/- Differential Voltage XOST Overshoot Conditions -0 100 Termination Across Conditions Am79C873 Min Typical Max Unit 0.4 V 2.4 V 0.4 V 2.4 V 1.5 2.0 2 -1.16 -0.90 -1 ...
Page 33
... TX Output Clock Frequency Tolerance t OSC Pulse Width High PWH OSC Pulse Width Low tPWL t RX_CLK Pulse Width High RPWH t RX_CLK Pulse Width Low RPWL Conditions 25 MHz Frequency 25 MHz Frequency Am79C873 Min Typical Max Unit 1.0 2.0 ns -0.5 0.5 ns -0.5 0.5 ns 300 ps ...
Page 34
... Note: 1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing tTX tTX pd Conditions 90% To 10%, Into 100 Differential Am79C873 t 2 tTX r/f 22164A-9 Typical ) Min (Note 1 Max Unit 11 - ...
Page 35
... RXI In To COL De-asserted Note: 1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing tRX tRX tTX Conditions Am79C873 22164A-10 Typical ) Min (Note 1 Max Unit ...
Page 36
... TX_EN Sampled To CRS De-asserted TX_EN Sampled To 10TXO Out (Tx tTX pd Latency Data Pulse Conditions DATA = 1 tTX tTX pd Conditions Am79C873 Clock Pulse FLP Burst 22164A-11 Min Typical Max Unit - 100 - 125 - 13.93 - ...
Page 37
... RXI In To RXD[0:3] Out (RX Latency) pd CRS Asserted To RXD[0:3], RX_DV, t1 RX_ER CRS De-asserted To RXD[0:3], RX_DV, t2 RX_ER t3 RXI In To CRS Asserted t4 RXI Quiet To CRS De-asserted tRX tRX Conditions Am79C873 22164A-13 Min Typical Max Unit ...
Page 38
... Figure 13. 10BASE-T Jab and Unjab Timing Diagram 10BASE-T Jab and Unjab Timing Parameters Symbol Parameter t1 Maximum Transmit Time t2 Unjab Time Conditions Conditions Am79C873 22164A-14 Min Typical Max Unit 0.65 1.3 1.6 ms 0.5 1.1 1.5 ms 22164A-15 Min Typical Max Unit 20 ...
Page 39
... MDIO Hold After MDC t3 MDC To MDIO Output Delay (Min) (Min 300 Conditions When OUTPUT By STA When OUTPUT By STA When OUTPTU By NetPHY-1 device Am79C873 22164A-16 22164A-17 Min Typical Max Unit 100 ns 39 ...
Page 40
... MHz, ±50 ppm or equivalent may be used. The crystal must be a fundamental type, parallel res- onant. Connect to X1 and X2, shunt each crystal lead to ground with an 18pf capacitor (see Figure 16). Y1 25M AGND Figure 16. Crystal Circuit Diagram Am79C873 32 OSC/XTLB 31 OSCGND AGND C18 ...
Page 41
... Transistor, NNP, General Purpose, 2N2222 Resistor, 470 , 5% Resistor, 820 , 5% Resistor Resistor, 510 , 5% Resistor, 6.01K , 1% Resistor, 49 Resistor, 1. Resistor Resistor, 10K , 5% NetPHY-1 device, PHY/Transceiver, 100 pin QFP Magnetics, Pulse Engineering, PE68515 Resistor Resistor Resistor 130 , 5% Resistor 300 Am79C873 Part Description , 5% 41 ...
Page 42
... R3 220 1.5K 220 Am79C873 NetPHY-1 C18 .1u R32 R33 GND 300 C23 .1u R36 FXSD R37 82 300 R38 62 FXRD- C26 R40 TP17 .1u 130 FXSD TP18 TP19 GND Am79C873 U1 50 FDXLED# 49 DVCC 48 CLK25M 47 LINKSTS DGND 44 RX_LOCK 43 SPEED10 42 UTP 41 TRIDRV 40 DVCC 39 DGND 38 DGND 37 DGND 36 BGRET ...
Page 43
... Physically place cap on SOLDER SIDE. VCC C19 # 01 C20 #7 C21 #8 C22 GND .1u #6 .01u .1u 10u #100 #11 GND L2 1uH Advanced Micro Devices Title NetPHY-1 Evaluation Board .1u Size Document Number B Date: Am79C873 VCC ...
Page 44
... Dimension D & not include resin fins. 2. Dimension GD & GE are for PC Board surface 3.30 Max. mount pad pitch design reference only. 0.10 Min. 3. All dimensions are based on metric system. 2.85 ±0.13 0.31 +0.10 -0.05 0.15 +0.10 -0.05 14.00 ±0.13 20.00 ±0.13 0.65 ±0.15 18.85 NOM. 17.60 NOM. 23.60 NOM. 18.80 ±0.31 24.79 ±0.31 1.19 ±0.20 2.41 ±0.20 0.15 Max Am79C873 ~12 L1 Detail F ...