AM79C960KCW Advanced Micro Devices, AM79C960KCW Datasheet
AM79C960KCW
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AM79C960KCW Summary of contents
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... Master and high-end machines that require local packet buffering for increased system latency. This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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AMD The PCnet-ISA controller is designed to directly inter- face with the ISA or EISA system bus. It contains an ISA bus interface unit, DMA Buffer Management Unit, IEEE 802.3 Media Access Control function, individual 136-byte transmit and 128-byte receive ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C960 K DEVICE NUMBER/DESCRIPTION Am79C960 PCnet -ISA Single Chip Ethernet Controller Valid Combinations AM79C960 ...
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AMD TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION RELATED PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD GENERAL PURPOSE SERIAL INTERFACE (GPSI) IEEE 1149.1 TEST ACCESS PORT INTERFACE Boundary Scan Circuit TAP FSM . . . . . . . . . . . . . . . . . . . . . . . ...
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LOOPBACK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD CSR66–67: Next Transmit Status and Byte Count CSR68–69: Transmit Status Temporary Storage CSR70–71: Temporary Storage CSR72: Receive Ring Counter CSR74: Transmit Ring Counter CSR76: Receive Ring Length CSR78: Transmit Ring Length CSR80: Burst and FIFO Threshold Control CSR82: Bus ...
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SYSTEM APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD BLOCK DIAGRAM: BUS MASTER MODE AEN DACK DRQ IOCHRDY IOCS16 IOR IOW ISA Bus IRQ Interface MASTER Unit MEMR MEMW REF RESET SBHE SMEMR SD0-15 Buffer LA17-23 Management SA0-19 Unit IOAM0-1 ISA SLEEP Config TE Control 1-352 P R ...
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CONNECTION DIAGRAM: BUS MASTER DVDD2 APCS 3 BPCS 4 LA17 5 6 LA18 7 LA19 DVSS3 8 9 LA20 10 LA21 11 LA22 12 LA23 SBHE 13 14 SA0 SA1 15 16 DVSS4 17 SA2 18 SA3 ...
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AMD PIN DESIGNATIONS: BUS MASTER Listed by Pin Number Pin # Name Pin # 1 DVDD2 APCS 3 33 BPCS LA17 35 6 LA18 36 7 LA19 37 8 DVSS3 38 9 LA20 ...
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PIN DESIGNATIONS: BUS MASTER Listed by Pin Name Name Pin # AEN 53 DVSS8 APCS 3 DVSS9 AVDD1 94 DVSS10 AVDD2 99 DVSS11 AVDD3 87 DVSS12 AVDD4 82 DXCVR AVSS1 91 IOAM0 AVSS2 89 IOAM1 BPCS 4 IOCHRDY IOCS16 CI– ...
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AMD PIN DESIGNATIONS: BUS MASTER Listed by Group Pin Name ISA Bus Interface AEN DACK DRQ IOCHRDY IOCS16 IOR IOW IRQ LA17-23 MASTER MEMR MEMW REF RESET SA0-19 SBHE SD0-15 SMEMR Board Interfaces APCS BPCS DXCVR IOAM0-1 LED0 LED1 LED2 ...
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PIN DESIGNATIONS: BUS MASTER (continued) Listed by Group Pin Name Attachment Unit Interface (AUI Twisted Pair Transceiver Interface (10BASE-T) RXD TXD TXP IEEE 1149.1 Test Access Port Interface (JTAG) TCK TDI TDO TMS Power Supplies AVDD AVSS ...
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AMD PIN DESCRIPTION: BUS MASTER MODE These pins are part of the bus master mode. In order to understand the pin descriptions, definition of some terms from a draft of IEEE P996 are included. IEEE P996 Terminology Alternate Master: Any ...
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BABL Babble RCVCCO Receive Collision Count Overflow JAB Jabber MISS Missed Frame MERR Memory Error MFCO Missed Frame Count Overflow RINT Receive Interrupt IDON Initialization Done TXSTRT Transmit Start LA17-23 Unlatched Address Bus The unlatched address bus is driven by ...
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AMD BPCS Boot PROM Chip Select This signal is asserted when the Boot PROM is read. If SA0-19 lines match a predefined address block and SMEMR is active and REF inactive, the BPCS signal will be asserted. The outputs of ...
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BLOCK DIAGRAM: SHARED MEMORY MODE AEN IOCHRDY IOR IOW ISA Bus IRQ Interface IOCS16 Unit MEMR MEMW RESET SBHE SD0-15 Buffer Management SA0-9 Unit IOAM0-1 ISA BPAM Config SMAM Control SMA SLEEP ...
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AMD CONNECTION DIAGRAM: SHARED MEMORY DVDD2 APCS 3 BPCS 4 SA0 5 6 SA1 7 SA2 DVSS3 8 9 SA3 10 SA4 11 SA5 12 SA6 SBHE 13 14 PRAB0 PRAB1 15 16 DVSS4 17 PRAB2 18 ...
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PIN DESIGNATIONS: SHARED MEMORY Listed by Pin Number Pin # Name Pin # 1 DVDD2 APCS 3 33 BPCS SA0 35 6 SA1 36 7 SA2 37 8 DVSS3 38 9 SA3 39 ...
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AMD PIN DESIGNATIONS: SHARED MEMORY Listed by Pin Name Name Pin # ABOE 38 DVSS8 AEN 53 DVSS9 APCS 3 DVSS10 AVDD1 94 DVSS11 AVDD2 99 DVSS12 AVDD3 87 DXCVR AVDD4 82 IOAM0 AVSS1 91 IOAM1 AVSS2 89 IOCHRDY BPAM ...
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PIN DESIGNATIONS: SHARED MEMORY Listed by Group Pin Name ISA Bus Interface AEN IOCHRDY IOCS16 IOR IOW IRQ MEMR MEMW RESET SA0-9 SBHE SD0-15 Board Interfaces ABOE APCS BPAM BPCS DXCVR IOAM0-1 LED0 LED1 LED2 LED3 MAUSEL/EAR PRAB0-15 PRDB0-7 SLEEP ...
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AMD PIN DESIGNATIONS: SHARED MEMORY (continued) Listed by Group Pin Name Attachment Unit Interface (AUI Twisted Pair Transceiver Interface (10BASE–T) RXD TXD TXP IEEE 1149.1 Test Access Port Interface (JTAG) TCK TDI TDO TMS Power Supplies AVDD ...
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PIN DESCRIPTION: SHARED MEMORY MODE ISA Interface AEN Address Enable This signal must be driven LOW when the bus performs an I/O access to the device. IOCHRDY I/O Channel Ready When the PCnet-ISA controller is being accessed, a HIGH on ...
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AMD SD0-15 System Data Bus This bus is used to transfer data to and from the PCnet- ISA controller to system resources via the ISA data bus. SD0-15 is driven by the PCnet-ISA controller when per- forming slave read operations. ...
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PRDB0-7 Private Data Bus This is the data bus for the static RAM, the Boot PROM, and the Address PROM. SLEEP Sleep When SLEEP input is asserted (active LOW), the PCnet-ISA controller performs an internal system reset and proceeds into ...
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AMD PIN DESCRIPTION: NETWORK INTERFACES AUI Interface CI+, CI– Control Input This is a differential input pair used to detect Collision (Signal Quality Error Signal). DI+, DI– Data In This is a differential receive data input pair to the PCnet- ...
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PIN DESCRIPTION: POWER SUPPLIES All power pins with a “D” prefix are digital pins connected to the digital circuitry and digital I/O buffers. All power pins with an “A” prefix are analog power pins connected to the analog circuitry. Not ...
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AMD FUNCTIONAL DESCRIPTION The PCnet-ISA controller is a highly integrated system solution for the PC-AT ISA architecture. It provides an Ethernet controller, AUI port, and 10BASE-T trans- ceiver. The PCnet-ISA controller can be directly interfaced to an ISA system bus. ...
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Shared Memory Mode System Interface The Shared Memory mode is the other fundamental op- erating mode available on the PCnet-ISA controller. The PCnet-ISA controller uses the same descriptor and buffer architecture as the LANCE, but these data struc- tures are ...
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AMD DETAILED FUNCTIONS Bus Interface Unit (BIU) The bus interface unit is a mixture MHz state ma- chine and asynchronous logic. It handles two types of accesses: accesses where the PCnet-ISA controller is a slave and accesses ...
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This means that the software must clear the descriptor own bits and reset its descriptor ring pointers before the restart of the PCnet-ISA controller. The reload of descriptor base addresses is performed in the LANCE only after initialization, so ...
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AMD 24-Bit Base Address Pointer to Initialization Block CSR2 IADR[23:16] RES Initialization Block MODE PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLEN RES RDRA[23:16] TDRA[15:0] TLEN RES TDRA[23:16] Polling When there is no channel activity and there is no ...
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A typical receive poll occurs under the following conditions: 1) PCnet-ISA controller does not possess ownership of the current RDTE and the poll time has elapsed and RXON = PCnet-ISA controller does not possess ownership of the ...
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AMD If the PCnet-ISA controller does own the second TDTE in a chain, it will gradually empty the contents of the first buffer (as the bytes are needed by the transmit opera- tion), perform a single-cycle DMA transfer to update ...
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In any case, lookahead will be performed to the third buffer and the information gathered will be stored in the chip, regardless of the state of the ownership bit the transmit flow, lookahead operations are per- formed ...
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AMD network is protected from gross errors due to inability of the host to keep pace with the MAC engine activity. On completion of transmission, the following transmit status is available in the appropriate TMD and CSR areas: The exact ...
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InterFrameSpacingPart1 is other than zero: (1) Upon completing a transmission, start timing the interpacket gap, as soon as transmitting and carrierSense are both false. (2) When timing an interpacket gap following re- ception, reset the interpacket gap timing ...
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AMD MAC Engine will abort the transmission, append the jam sequence, and set the LCOL bit. No retry attempt will be scheduled on detection of a late collision, and the FIFO will be flushed. The IEEE 802.3 Standard requires use ...
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Transmitter Timing and Operation A 20 MHz fundamental-mode crystal oscillator provides the basic timing reference for the MENDEC portion of the PCnet-ISA controller. The crystal input is divided by two to create the internal transmit clock reference. Both clocks are ...
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AMD PLL Tracking After clock acquisition, the phase-locked clock is com- pared to the incoming transition at the bit cell center (BCC) and the resulting phase error is applied to a cor- rection circuit. This circuit phase-locked clock remains locked ...
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Twisted Pair Transceiver (T-MAU) The T-MAU implements the Medium Attachment Unit (MAU) functions for the Twisted Pair Medium, as speci- fied by the supplement to IEEE 802.3 standard (Type 10BASE-T). The T-MAU provides twisted pair driver and receiver circuits, including ...
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AMD Negative link beat pulses are defined as transmitted sig- nals with a negative amplitude greater than 585 mV with a pulse width of 60 ns–200 ns. This negative excursion may be followed by a positive excursion. This definition is ...
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EADI (External Address Detection Interface) This interface is provided to allow external address filter- ing selected by setting the EADISEL bit in ISACSR2. This feature is typically utilized for terminal servers, bridges and/or router type products. The use ...
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AMD General Purpose Serial Interface (GPSI) The PCnet-ISA controller contains a General Purpose Serial Interface (GPSI) designed for testing the digital portions of the chip. The MENDEC, AUI, and twisted pair interface are by-passed once the device is set up ...
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IEEE 1149.1 Test Access Port Interface An IEEE 1149.1 compatible boundary scan Test Access Port is provided for board-level continuity test and diag- nostics. All digital input, output, and input/output pins are tested. Analog pins, including the AUI differential driver ...
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AMD Power Savings Modes The PCnet-ISA controller supports two hardware power-savings modes. Both are entered by asserting the SLEEP pin LOW. In coma mode, the PCnet-ISA controller will go into deep sleep with no support to automatically wake itself up. ...
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All accesses to 8-bit resources (which do not return MEMCS16 or IOCS16) use SD0- odd byte is ac- cessed, the Current ...
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AMD Refresh Cycles Although the PCnet-ISA controller is neither an origina- tor or a receiver of refresh cycles, it does need to avoid unintentional activity during a refresh cycle in bus mas- ter mode. A refresh cycle is performed as ...
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Current Master Operation Current Master operation only occurs in the bus master mode. It does not occur in shared memory mode. There are three phases to the use of the bus by the PCnet-ISA controller as Current Master, the Obtain ...
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AMD Shared Memory Mode Address PROM Cycles The Address PROM is a small (16 bytes) 8-bit PROM connected to the PCnet-ISA controller Private Data Bus (PRDB). The PCnet-ISA controller will support only 8-bit ISA I/O bus cycles for the address ...
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The PCnet-ISA controller will perform 8-bit ISA bus cy- cle operation for all resource (registers, PROMs, SRAM) if SBHE has been left unconnected, such as in the case of an 8-bit system like the PC/XT. The BPCS signal generated by ...
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AMD The address and SROE go active within the clock going HIGH. Data is required to be valid 5 ns be- fore the end of the second clock cycle. Address and SROE have hold ...
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It is the responsibility of upper layer software to correctly define the actual length field contained in the message to correspond to the total number of LLC Data bytes en- capsulated in the packet (length field as defined in the ...
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AMD the completion of transmission, then the PCnet-ISA controller will set the CERR bit in CSR0. CERR will be asserted in 10BASE-T mode after transmit if T-MAU is in Link Fail state. CERR will never cause INTR to be acti- ...
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Receive FCS Checking Reception and checking of the received FCS is per- formed automatically by the PCnet-ISA controller. Note that if the Automatic Pad Stripping feature is enabled, the received FCS will be verified against the value com- puted for ...
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AMD Each status signal is ANDed with its corresponding enable signal. The enabled status signals run to a com- mon OR gate: COL COL E JAB JAB E LNK LNK E RCV RCV E RVPOL RVPOL E XMT XMT E ...
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PCnet-ISA CONTROLLER REGISTERS The PCnet-ISA controller implements all LANCE (Am7990) registers, plus a number of additional regis- ters. The PCnet-ISA controller registers are compatible with the original LANCE, but there are some places where previously reserved LANCE bits are now ...
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AMD MERR assertion will set the ERR bit. MERR is set by the Bus Interface Unit and cleared by writing a “1”. Writing a “0” has no effect. MERR is cleared by RESET or by setting the STOP bit. 10 ...
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STOP STOP assertion disables the chip from all external activity. The chip remains inactive until either STRT or INIT are set. If STOP, STRT and INIT are all set to- gether, STOP will override STRT and INIT. STOP is ...
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AMD 4 DXMT2PD Disable Transmit Deferral. If DXMT2PD is set, Transmit Two Part Deferral will be disabled. DXMT2PD is cleared by RESET and is not affected by STOP. 3 EMBA Enable Modified Algorithm. If EMBA is set, a modi- fied ...
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TXSTRT is set by the MAC Unit and cleared by writing a “1”, set- ting RESET or setting the STOP bit. Writing a “0” has no effect. 2 TXSTRTM Transmit TXSTRTM is set, the TXSTRT bit in CSR4 will be ...
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AMD Read/write accessible only when STOP bit is set. CSR12: Physical Address Register, PADR[15:0] Bit Name Description 15-0 PADR[15:0] Physical Address PADR[15:0]. Undefined until in- itialized either automatically by loading the initialization block or directly by an I/O write to ...
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Transmit Mode Select (AUI Mode only) LRT Low Receive Threshold. When LRT = “1”, the internal twisted pair receive thresholds are re- duced by 4.5 dB below the standard 10BASE-T value (ap- proximately unsquelch threshold for the RXD circuit will ...
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AMD In loopback mode, this bit deter- mines if the transmitter appends FCS or if the receiver checks the FCS. This bit was called DTCR in the LANCE (Am7990). Read/write accessible only when STOP bit is set. 2 LOOP Loopback ...
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Read/write accessible only when STOP bit is set. CSR24-25: Base Address of Receive Ring Bit Name Description 31-24 RES Reserved locations. Written as zero and read as undefined. 23-0 BADR Contains the base address ...
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AMD Read/write accessible only when STOP bit is set. 23-12 RES Reserved locations. Written as zero and read as undefined. 11-0 CRBC Current Receive Byte Count. This field is a copy of the BCNT field of RMD2 of the current ...
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CSR50-51: Temporary Storage Bit Name Description 31-0 TMP1 Temporary Storage location. Read/write accessible only when STOP bit is set. CSR52-53: Temporary Storage Bit Name Description 31-0 TMP2 Temporary Storage location. Read/write accessible only when STOP bit is set. CSR54-55: Temporary ...
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AMD CSR68-69: Transmit Status Temporary Storage Bit Name Description 31-0 XSTMP Transmit Status Temporary Stor- age location. Read/write accessible only when STOP bit is set. CSR70-71: Temporary Storage Bit Name Description 31-0 TMP8 Temporary Storage location. Read/write accessible only when ...
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RCVFW[1:0] Bytes Received 11-10XMTSP[1:0] Transmit Start Point. XMTSP controls the point at which pre- amble transmission commence in relation to the num- ber of bytes written to the transmit FIFO for the current transmit frame. When ...
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AMD ENTST bit in CSR4 is set, all writes to this register will auto- matically perform a decrement cycle. When the Bus Activity Timer reg- ister (CSR82: enabled, the PCnet-ISA control- ler will relinquish the bus when either the time ...
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CSR96-97: Bus Interface Scratch Register 0 Bit Name Description 31-0 SCR0 This register is shared between the Buffer Management Unit and the Bus Interface Unit. All De- scriptor Data communications between the BIU and BMU are written and read through ...
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AMD 15-5 RES Reserved locations. Written as zero and read as undefined. 4 GPSIEN This mode places the PCnet-ISA controller in the GPSI Mode. This mode will reconfigure the Exter- nal Address Pins so that the GPSI port is exposed. ...
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EADISEL EADI Select. Enables EADI match mode. XMAUSEL must AWAKE Auto-Wake. If LNKST is set and AWAKE = “1”, the 10BASE-T receive circuitry is active during ...
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AMD ISACSR6: LED2 Status Bit Name Description ISACSR6 controls the func- tion(s) that displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the logical OR of the en- abled functions. defaults to twisted ...
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Initialization Block The figure below shows the Initialization Block memory configuration. Note that the Initialization Block must be based on a word (16-bit) boundary. Bits Bits Address 15–12 11–8 IADR+22 TLEN RES IADR+20 TDRA 15–00 IADR+18 RLEN RES IADR+16 RDRA ...
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AMD Received Message Destination Address MATCH = 1: Packet Accepted MATCH = 0: Packet Rejected The Logical Address Filter is used in multicast address- ing schemes. The acceptance of the incoming frame based on the filter value ...
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ERR ERR is the OR of FRAM, OFLO, CRC, or BUFF. ERR is written by the PCnet-ISA controller. 13 FRAM FRAMING that the incoming frame con- tained a ...
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AMD Note that bit 13 of TMD1, which was formerly a reserved bit in the LANCE (Am7990), is assigned a new meaning, ADD_FCS. TMD0 Holds LADRF [15:0]. This is combined with HADR [7:0] in TMD1 to form a 24-bit address ...
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PCnet-ISA controller. There are no minimum buffer size re- strictions. Zero length buffers are allowed for protocols which re- quire it. TMD3 Bit Name Description 15 BUFF BUFFER ERROR is set by the PCnet-ISA transmission PCnet-ISA controller does not ...
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AMD Register Summary Ethernet Controller Registers (accessed via RDP port) RAP Addr Symbol 00 CSR0 01 CSR1 02 CSR2 03 CSR3 04 CSR4 05 CSR5 06 CSR6 07 CSR7 08 CSR8 09 CSR9 10 CSR10 11 CSR11 12 CSR12 13 ...
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Register Summary Ethernet Controller Registers (accessed via RDP port) (continued) RAP Addr Symbol 64–65 CSR64 66–67 CSR66 68–69 CSR68 70–71 CSR70 72 CSR72 74 CSR74 76 CSR76 78 CSR78 80 CSR80 82 CSR82 84–85 CSR84 86 CSR86 88–89 CSR88 92 ...
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AMD Register Summary ISACSR—ISA Bus Configuration Registers (ac- cessed via IDP port) RAP Addr Mnemonic 0 MSRDA 1 MSWRA Reserved 4 LED0 5 LED1 6 LED2 7 LED3 I/O Address Offset Offset #Bytes Register 0h 16 Address ...
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SYSTEM APPLICATION ISA Bus Interface Compatibility Considerations Although 8 MHz is now widely accepted as the standard speed at which to run the ISA bus, many machines have been built which operate at higher speeds with non- standard timing. Some ...
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AMD 16-Bit System Data System Address ISA ABOE BPAM SMAM Bus E Address Address Compare Address PROM Interface The suggested address PROM is the Am27LS19, a 32x8 device. APCS should be connected directly to the device’s G input. A4–A0 27LS19 ...
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Interface The diagram below shows the proper 10BASE-T net- work interface design. Refer to the PCnet-Family TXD+ TXP+ PCnet-ISA TXD- PCnet-ISA Controller TXP- RXD+ RXD- Note: Note : All resistors ±1% All resistors are 1% 10BASE-T External Components and ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . ...
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DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued) Parameter Symbol Parameter Description Attachment Unit Interface (Continued) I Transmit Differential AODOFF Output Idle Current V Transmit Output Common CMT Mode Voltage V DO Transmit Differential ODI Output Voltage Imbalance ...
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AMD DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued) Parameter Symbol Parameter Description Twisted Pair Interface (continued) V RXD Switching Threshold RXDTH V TXD and TXP Output TXH HIGH Voltage V TXD and TXP Output TXL LOW Voltage ...
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SWITCHING CHARACTERISTICS: BUS MASTER MODE Parameter Symbol Parameter Description Input/Output Write Timing AEN, SBHE, SA0–9 Setup t IOW1 IOW to AEN, SBHE,SA0–9 Hold t IOW2 IOW After IOW Assertion t IOW3 IOW Inactive t IOW4 IOW t SD Setup to ...
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AMD SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued) Parameter Symbol Parameter Description Master Mode Bus Release t Command Deassert to MMBR1 DACK t DRQ to MMBR2 MASTER t DRQ to MMBR3 DRQ to Command, SBHE, t MMBR4 SA0–19, LA17–23 Tristated, Master ...
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SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued) Parameter Symbol Parameter Description Master Mode Address PROM Read IOR to APCS t MA1 APCS Active t MA2 APCS t PRDB Setup to MA3 APCS t PRDB Hold After MA4 APCS to t IOCHRDY ...
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AMD SWITCHING CHARACTERISTICS: SHARED MEMORY MODE Parameter Symbol Parameter Description Input/Output Write Timing AEN, SBHE, SA0–9 Setup t IOW1 IOW to AEN, SBHE,SA0–9 Hold t IOW2 IOW After IOW Assertion t IOW3 IOW Inactive t IOW4 IOW t SD Setup ...
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SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued) Parameter Symbol Parameter Description Memory Read Timing t SA0–9, PRAB10–15, MR1 SBHE, SMAM/BPAM MEMR Setup to SA0–9, PRAB10–15, SBHE, t MR2 SMAM/BPAM Hold After MEMR MEMR Inactive t MR3 MEMR t SD Hold After ...
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AMD SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued) Parameter Symbol Parameter Description SRAM Read/Write, Boot PROM Read, Address PROM Read on Private Bus (continued) t PRDB Setup to PRAB PR8 Change, APROM Access t PRDB Hold After PRAB PR9 Change, APROM ...
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SWITCHING CHARACTERISTICS: EADI Parameter Symbol Parameter Description t SRD Setup to SRDCLK EAD1 t SRD Hold to SRDCLK EAD2 SF/BD Change to t SRDCLK EAD3 EAR Deassertion to t EAD4 SRDCLK (First Rising Edge) EAR Assertion After SFD t EAD5 ...
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AMD SWITCHING CHARACTERISTICS: GPSI Parameter Symbol Parameter Description Transmit Timing t TCLK Period (802.3 Compliant) GPT1 t TCLK HIGH Time GPT2 t TX and TENA Delay from GPT3 t RENA Setup Before GPT4 t RENA Hold After GPT5 t CLSN ...
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SWITCHING CHARACTERISTICS: AUI Parameter Symbol Parameter Description AUI Port t DO+,DO- Rise Time (10% to 90%) DOTR t DO+,DO- Fall Time (90% to 10%) DOTF t DO+,DO- Rise and Fall Time Mismatch DORM t DO+/- End of Transmission DOETD t ...
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AMD SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE Parameter Symbol Parameter Description Transmit Timing t Transmit Start of Idle TETD t Transmitter Rise Time TR t Transmitter Fall Time TF t Transmitter Rise and Fall TM Time Mismatch t Idle Signal Period PERLP ...
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KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUITS Sense Point WAVEFORM INPUTS Must Be Steady May Change from May Change from Don’t Care Any ...
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AMD SWITCHING TEST CIRCUITS DO+ DO– TXD+ TXD– Includes Test Jig Capacitance TXP+ TXP– Includes Test Jig Capacitance 1-444 52.3 TEST POINT 154 100 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE AEN, SBHE, SA0–9 IOW SD AEN, SBHE, SA0–9 IOW IOCHRDY Stable t IOW1 t IOW3 t IOW5 I/O Write without Wait States Stable ...
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AMD SWITCHING WAVEFORMS: BUS MASTER MODE AEN, SBHE, SA0–9 IOR SD AEN, SBHE, SA0–9 IOR IOCHRDY SD 1-446 Stable t IOR1 t IOR5 Stable I/O Read without Wait States ...
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SWITCHING WAVEFORMS: BUS MASTER MODE IOW, MEMW SMEMR, MEMR, IOR AEN, SBHE, SA0–9 IOCS16 REF DRQ t DACK t MMA3 MASTER MEMR/MEMW SBHE, SA0–19, LA17– IOM1 I/O to ...
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AMD SWITCHING WAVEFORMS: BUS MASTER MODE DRQ DACK MASTER MEMR/MEMW SBHE, SA0–19, LA17–23 (Non Wait) SBHE, SA0–19, LA17–23 t MMW1 MEMW IOCHRDY t MMW10 SD0–15 1-448 MMBR1 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE (Non Wait) SBHE, SA0–19, LA17–23 t MMR1 MEMR IOCHRDY SD0–15 AEN, SBHE, SA0–9 IOR IOCHRDY APCS PRDB0–7 SD0– MMR5 MMR6 Stable t ...
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AMD SWITCHING WAVEFORMS: BUS MASTER MODE REF, SBHE, SA0–19 SMEMR IOCHRDY BPCS PRDB0–7 SD0–7 1-450 Stable t MB1 t MB3 t MB5 t MB6 t MB8 Boot PROM Read ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE AEN, SBHE, SA0–9 IOW SD AEN, SBHE, SA0–9 t IOW IOCHRDY Stable t t IOW1 IOW3 I/O Write without Wait States Stable IOW1 ...
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AMD SWITCHING WAVEFORMS: SHARED MEMORY MODE AEN, SBHE, SA0–9 IOR SD AEN, SBHE, SA0–9 IOR IOCHRDY SD 1-452 Stable t IOR1 t IOR5 Stable I/O Read without Wait States ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE SA0–9, PRAB10–15, SBHE SMAM MEMW SD SA0–9, PRAB10–15, SBHE SM_AM t MEMW IOCHRDY Stable t t MW1 MW3 Memory Write without Wait States ...
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AMD SWITCHING WAVEFORMS: SHARED MEMORY MODE SA0–9, PRAB10–15, SBHE SMAM MEMR SD SA0–9, PRAB10–15, SBHE SMAM/BPAM MEMR IOCHRDY SD 1-454 Stable t MR1 t MR5 Stable Memory Read without ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE IOW, MEMW SMEMR, MEMR, IOR AEN, SBHE, SA0–9 IOCS16 IOM1 I/O to Memory Command Inactive Time t IOCS1 IOCS16 Timings Am79C960 AMD t ...
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AMD SWITCHING WAVEFORMS: SHARED MEMORY MODE ABOE t PR1 t PR2 PRAB10–15 PRAB0–9 SRWE PRDB ABOE t PR1 t PR2 PRAB10–15 PRAB0–9 SROE PRDB 1-456 PR13 t PR14 ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE ABOE t PR1 t PR2 PRAB10–15 PRAB0–9 BPCS PRDB ABOE PRAB10–15 PRAB0–9 APCS PRDB PR10 t t PR11 PR12 Boot PROM Read on ...
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AMD SWITCHING WAVEFORMS: GPSI (First Bit Preamble) tGPT1 tGPT2 Transmit Clock (STDCLK) tGPT3 Transmit Data (TXDAT) tGPT3 Transmit Enable (TXEN) Carrier Present (RXCRS) (Note 1) Collision (CLSN) (Note 2) Notes RXCRS is not present during transmission, LCAR bit ...
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SWITCHING WAVEFORMS: EADI SRDCLK (LED3) One Zero One SRD (LED2) t EAD1 t EAD2 SF/BD (LED1) t EAD4 EAR (MAUSEL) SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE TCK t t JTG3 JTG4 TDI t JTG5 TMS TDO ...
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AMD SWITCHING WAVEFORMS: AUI XTAL1 t XI ISTDCLK (Note 1) ITXEN (Note 1) 1 ITXDAT+ (Note 1) DO+ DO– DO Note: 1. Internal signal and is shown for clarification only. XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ ...
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SWITCHING WAVEFORMS: AUI XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ (Note 1) DO+ DO– Bit (n–2) Note: 1. Internal signal and is shown for clarification only. Transmit Timing—End of Packet (Last Bit = 1) P ...
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AMD SWITCHING WAVEFORMS: AUI DI+/– V ASQ t PWKDI t PWODI CI+/– V ASQ t PWOCI DO+/– 1-462 Receive Timing Diagram t PWKCI Collision Timing Diagram t DOETD 40 ...
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SWITCHING WAVEFORMS: 10BASE-T INTERFACE TXD+ TXP+ TXD– TXP– XMT t PWPLP TXD+ TXP+ TXD– TXP– t PWLP Transmit Timing t PERLP Idle Link Test Pulse ...
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AMD SWITCHING WAVEFORMS: 10BASE-T INTERFACE RXD RXD 1-464 Receive Thresholds (LRT = 0; CSR15[9]) Receive Thresholds (LRT = 1; CSR15[9]) Am79C960 V TSQ+ V THS+ V THS– V TSQ– ...
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APPENDIX A PCnet-ISA Compatible Media Interface Modules PCnet-ISA COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS The table below provides a sample list of PCnet-ISA compatible 10BASE-T filter and transformer modules Manufacturer Part No. Bel Fuse A556-2006-DE 16-pin 0.3” DIL Bel Fuse 0556-2006-00 ...
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AMD PCnet-ISA Compatible DC/DC Converters The table below provides a sample list of PCnet-ISA compatible DC/DC converters available from various Manufacturer Part No. Halo Electronics DCU0-0509D Halo Electronics DCU0-0509E PCA Electronics EPC1007P PCA Electronics EPC1054P PCA Electronics EPC1078 Valor Electronics ...
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APPENDIX B Recommendation for Reducing Noise Injection DECOUPLING LOW-PASS R/C FILTER DESIGN The PCnet-ISA controller is an integrated, single-chip Ethernet controller, which contains both digital and ana- log circuitry. The analog circuitry contains a high speed Phase-Locked Loop (PLL) and ...
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AMD 6.8 F VDD Plane AVDD2 Pin 99 AVSS2 Pin PCnet-ISA To determine the value for the resistor and capacitor, the formula is Where ohms and ...
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APPENDIX C Alternative Method for Initialization The PCnet-ISA controller may be initialized by perform- ing I/O writes only. That is, data can be written directly to the appropriate control and status registers (CSR) instead of reading from the Initialization Block ...