AM79C983A Advanced Micro Devices, AM79C983A Datasheet
AM79C983A
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AM79C983A Summary of contents
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... Section 9 ( Repeater Unit ) and Section19 ( Layer Management for 10 Mb/s Baseband Repeaters ) of the IEEE 802.3 standard. The Am79C983A IMR2 device provides 1 standard Attachment Unit Interface (AUI) port, 12 Pseudo Attachment Unit Interface (PAUI) por ts, and 1 Reversible AUI (RAUI) port for direct connection to a media access controller (MAC) ...
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... IMR2 device that transfers the information to a MAC For application examples on building fully-managed repeaters using the IMR2 and QuIET devices, refer to AMD’s IMR2 Technical Manual (PID 19898A). Am79C983A ...
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... RST XENA Manchester Decoder PLL Control Manchester Encoder IMR2 Repeater Engine Attributes and Control Registers (HIMIB) Receiver MAC Engine Am79C983A FIFO Preamble Jam FIFO DAT REQ ACK COL JAM ECLK MACEN FRAME XMODE LD[7:0] BSEL CRS COLX ...
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... Am79C970 PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus) Am79C970A PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems Am79C983A ...
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... PCLK 23 DVSS PENAO 24 PENAI 25 26 DVSS MATCHI 27 MATCHO VDD INT 31 32 RDY 33 DVSS PQFP Am79C983 A Am79C983A 99 RDO– 98 RDO+ 97 RCI– 96 RCI+ 95 DVSS 94 DIR[1] 93 DIR[0] 92 SDATA[3] 91 DVSS 90 SDATA[2] 89 SDATA[1] 88 SDATA[0] VDD 87 XENA 86 RST ...
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... PTAG PDRV D[7:0] MCLK CS RST C/D XENA RD XMODE WR RDY INT SDATA [3:0] DIR [1: Expansion Packet Bus Report Port Repeater State Machine PAUI Port 11 Am79C983A Expansion Bus LED Interface Microprocessor Interface Transceiver Interface 19879B-3 MAC Engine Transceiver Interface Microprocessor Interface LED Interface 19879B-4 ...
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... S = Security included. (See Appendix.) DEVICE NUMBER/DESCRIPTION Am79C983A Integrated Multiport Repeater 2 (IMR2) Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C983A Valid Combinations 7 ...
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... QuIET Device Control and Status Data Interface ................................................................... 26 QuIET Device Control and Status Data Interface Operation ........................................... 26 Control and Status for Non-QuIET Transceivers ............................................................. 27 Visual Status Monitoring (LED) Support ....................................................................................... 27 Using AUI/RAUI for 10BASE-T Ports ..................................................................................... 28 Intrusion Protection ....................................................................................................................... 28 Timer Values .......................................................................................................................... Am79C983A ...
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... Port Switching Control.............................................................................................. 37 Extended Distance Enable....................................................................................... 38 Automatic Last Source Address Intrusion Control ................................................... 38 Automatic Preferred Source Address Intrusion Control ........................................... 38 Last Source Address Lock Control........................................................................... 38 Register Bank 4: Port Status Registers ........................................................................... 39 Partitioning Status of Ports....................................................................................... 39 Link Test Status of Ports .......................................................................................... 39 Loopback Error Status ............................................................................................. 39 Receive Polarity Status ............................................................................................ 39 Am79C983A 9 ...
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... PR Port Configuration ............................................................................................................ 45 Port Switching ............................................................................................................................... 48 ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 50 OPERATING RANGES................................................................................................................. 50 DC CHARACTERISTICS over operating ranges unless otherwise specified............................... 50 SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified ............... 51 KEY TO SWITCHING WAVEFORMS................................................................................................ 54 SWITCHING WAVEFORMS .............................................................................................................. 54 Master Clock (MCLK) Timing........................................................................................................ Am79C983A ...
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... Packet Report Port Timing............................................................................................................ 56 Expansion Port Input Timing - Asynchronous Mode..................................................................... 56 Expansion Port Output Timing - Asynchronous Mode .................................................................. 57 PAUI PDO Transmit...................................................................................................................... 57 PAUI PCI Receive......................................................................................................................... 57 PAUI Receive................................................................................................................................ 58 (R)AUI Timing ................................................................................................................................ 58 (R)AUI Receive ............................................................................................................................. 58 Microprocessor Bus Interface Timing ........................................................................................... 59 PHYSICAL DIMENSIONS.................................................................................................................. Am79C983A 11 ...
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... PDO[3] 92 SDATA[3] PDO[2] 93 DIR[ DIR[1] DD PDO[ PDO[0] 96 RCI+ LD[0] 97 RCI- LD[1] 98 RDO RDO- Am79C983A Pin No. Pin Name AV 100 SS 101 RDI+ 102 RDI- SS 103 V DD 104 PDI[0] 105 PCI[0] SS 106 PDI[1] 107 PCI[1] 108 PDI[2] 109 PCI[2] DD 110 PDI[3] ...
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... Input, Active LOW When this signal is asserted by an external arbiter, it signals to the requesting IMR2 device that it may drive the DAT and JAM pins. It signals to other IMR2 devices the presence of valid collision status on the JAM line and valid data on the DAT line. Am79C983A 13 ...
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... PDRV is TRUE when the IMR2 device is transmitting data over PDAT second packet arrives before PDAT is finished transmitting status, PDRV goes FALSE after the status is transmitted. PCLK Packet Report Clock Output, High Impedance PCLK is a 10-MHz clock. PDAT transitions are synchro- nized to PCLK. Am79C983A Default ...
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... SDATA [3:0] Serial Data Input/Output SDATA carries command and status data between the IMR2 device and the QuIET device (or other connected transceiver). Pin Transceiver Ports SDATA [0] PAUI [3:0] SDATA [1] PAUI [7:4] SDATA [2] PAUI [11:8] SDATA [3] Arbitrary ports Am79C983A through P ). When 7 0 through P ), the AUI ...
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... DV ss Digital Ground Ground Pin These pins provide the ground reference for the digital portions of the IMR2 circuitry. These pins should be de- coupled and kept separate from the analog power plane. Am79C983A ...
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... FUNCTIONAL DESCRIPTION Overview The Am79C983A Integrated Multiport Repeater 2 de- vice provides a system-level solution to designing IEEE 802.3 managed repeaters. It includes 12 pseudo AUI (PAUI) ports for single-ended connections to external transceivers. The IMR2 device interfaces directly with AMD's Am79C988A Quad Integrated Ethernet Trans- ceiver (QuIET) device for 10BASE-T implementations. ...
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... The IMR2 device generates status information on every packet that it repeats. The data is transmitted over the Packet Report Port. The data format consists of the beginning of the packet followed by a packet tag and statistical data on the packet. Preamble DA SA T/L Packet Data P1 P0 LSB Am79C983A LSB R 0 Port No ...
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... Bank Select ICR PCR C Data (D) Port Am79C983A 27, 28, 29, 30 RMN MSR P11, A, AR, EP 19879B-5 19 ...
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... Data Rate Mismatch Interrupt Enable Last Source Address Compare Enable Preferred Address Compare Enable Transceiver Interface Changed Interrupt Enable Jabber Interrupt Enable Am79C983A Register Bank 3 Port Control Registers Alternative Partition Algorithm Enable Link Test Enable Link Pulse Transmit Enable Automatic Receiver ...
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... Octets etherStats256to511- Octets etherStats512to1023- Octets etherStats1024to1518- Octets Activity Am79C983A Register Bank 16-30 Port Attribute Registers Readable Frames Readable Octets Frame Check Sequence Errors Alignment Errors Frames Too Long Short Events Runts Collisions Late Events Very Long Events ...
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... MAC. The pin MACEN selects the MAC mode. When MACEN is TRUE (LOW), the statistics on the data re- ceived by DAT are recorded in the management regis- ters. The expansion bus is considered another port in the same sense as the PAUIs, the AUI, and the RAUI. Am79C983A ...
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... IMR2 device collision state. Arbitration for control of the bussed signals, DAT and JAM, is provided by external circuitry. One output pin (REQ) and two input pins (ACK and COL) are used as arbitration signals. The IMR2 device asserts REQ to Am79C983A Default M Masked M,R ...
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... MAC. Therefore, packet compression is automati- cally disabled when the destination address of the packet is a valid address for the expansion bus. How- ever, the report tag is appended to the end of the packet. Note that the entire packet is also sent if the destination address is a broadcast address. Am79C983A 19879B-6 ...
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... RDO and RDI does not change with the configuration. Therefore, in the reverse configuration RDO should be connected the MAC and RDI should be con- nected the MAC. 19879B-7 Table 3. RAUI Port Device Configuration Register Bit Am79C983A RAUI Port Mode Normal Mode Reverse Mode (RCI is an Output) 25 ...
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... Non-QuIET device mode. The QuIET device mode is automatically selected when a QuIET device is attached and used, and the Non-QuIET mode is selected when another type of transceiver is used. Note that it is possible for different sets of ports to use different types of transceivers. Am79C983A Stat2 Field FCS 19879B-8 Port PAUI [3:0] ...
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... Monitoring port continually cycles as per 5. Each strobe is active for 64-bit times (6.4 s). This allows a 10-per- cent duty cycle. The following table gives the value of LD[7:0] corresponding to the Attribute Select signal. Signal CRS COLX PART LINK POL Am79C983A Action 00 Select Transceiver 0. 01 Select Transceiver 1. 10 Select Transceiver 2. 11 Select Transceiver 3. ...
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... Source Address Changed Interrupt compares the incoming packet's source address against two registers: Last Source Address Register and the Pre- ferred Source Address Register. The interrupt is set when the source address of the incoming packet does not match both registers. Intruder Interrupt compares Am79C983A EN EN 19879B-10 ...
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... These registers are each two bytes long. Each bit corresponds to an individual port. Active statistics will be maintained on the data received by DAT only if the EP bit of the Port Enable Register is set and MACEN is TRUE. Am79C983A into the C port, where P ...
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... Enable bit is enabled, then the INT output pin is driven LOW. The set bit(s) in the Source Address Match Interrupt Registers are cleared when these reg- isters are read. Note: Once the sequence is started, all six bytes have to be written or the contents do not change. Am79C983A values of reserved 1110 1010 bits ...
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... MSB Transceiver 0 Transceiver 1 Transceiver 2 Transceiver 3 This 16-bit register is divided into four sections. Each section is labeled M ceivers 0 through 3. These register bits are only valid if the appropriate Transceiver Interface Status Register bit indicates that a QuIET device is connected. Am79C983A LSB ...
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... This register is only valid when a QuIET device is connected to the corresponding port(s). D Port Read TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 Byte 0 Byte 1 SP3 MSB Am79C983A 1110 0000 RAUI ...
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... When the source address of an incoming packet from any port matches the Source Address Match Register, P8 the appropriate bit is set. The received packet must be LSB an error-free packet. D Port Read P7 Byte 0 Byte 1 0 MSB Am79C983A RAUI AUI P11 P10 P9 P8 ...
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... SFD), but is other- LSB wise well formed and error free. D Port Read/Write P7 Byte 0 Byte 1 0 MSB Am79C983A 1111 0001 TP11 TP 10 TP9 TP8 0 Port does not jabber 1 Port in jabber 1110 0000 ...
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... The management system can then take appropriate ac- TP9 TP8 10 tion, such as disabling the corresponding port. LSB Change Interrupt D Port Read/Write P7 Byte 0 Byte 1 0 MSB Pn/AUI/RAUI Am79C983A RAUI AUI P11 P10 P9 0 SQE Test Error Change ...
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... When a bit in this register is set, an indication of jabber from a port will cause an interrupt Port Read/Write LSB TP7 Byte 0 Byte 1 SP3 SP2 SP1 SP0 MSB Address TPn/SPn Am79C983A Preferred Source Address Compare disabled ...
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... Port Switching Control Address: 1110 0111 Setting a bit in this register isolates the corresponding port. All input signals to the corresponding port and all information concerning port activity from the transceiver Am79C983A TP5 TP4 TP3 TP2 TP1 TP0 TP11 TP 10 TP9 TP8 LSB ...
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... Last Source Address Lock Control will not comply with IETF RFC 1516. D Port Read/Write Byte 0 P8 Byte 1 0 LSB MSB Am79C983A 0 Automatic Intrusion Control with Last Source Address disabled 1 Automatic Intrusion Control with Last Source Address enabled 1110 1010 ...
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... FCS bits) by the IMR2 device etherStatsPkts P8 Address: LSB The value in this register represents the total number of packets received by the IMR2 device. Am79C983A 1110 0100 TP11 TP 10 TP9 TP8 0 Polarity correct 1 Polarity reversed 1110 0101 P6 ...
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... The ac- cess can jump to the next level of the FIFO in the middle of a read by writing any value to the node processor port with the C/D pin HIGH. If the node processor port is ac- cessed (with the C/D pin LOW) after the last byte is read, Am79C983A ...
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... When writing the Last Source Address Register and the Preferred Source Register, if the sequence is aborted prior to the 6th consecutive write cycle, the register value is not altered. The sequence (read or write) may be aborted and restarted by programming the C register. Am79C983A ...
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... Byte 3 MSB Frames Too Long is a read-only attribute that counts the number of frames that exceed the maximum valid packet length of 1518 bytes. This attribute is a 32-bit counter with a minimum rollover time of 61 days. Am79C983A bit 0 bit 24 LSB bit 0 bit 24 LSB ...
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... The attribute is a 32-bit counter with a min- imum rollover time of 80 hours. Note: The rate at which the Data Rate Mismatches attribute will increment will depend on the magnitude of the difference between the received signal clock and the local transmit frequency. Am79C983A bit 0 bit 24 LSB bit 0 bit ...
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... The address programmed into this register is compared bit 24 with the incoming source address to generate a Source LSB Address Changed Interrupt. This is a 6-byte word. The operation will abort if all 6 bytes are not written. bit 0 bit 40 LSB Am79C983A bit 0 bit 24 LSB bit 0 bit 40 LSB ...
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... Here the IMR2 device is connected to the SIA interface of the Am79C90 (C-LANCE). MACEN, DAT, and ECLK are bus signals. Therefore, the AND gates and buffers to these signals must be open-collector or open-drain. The OR gate for RENA satisfies the loopback require- ments for the C-LANCE. Am79C983A 45 ...
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... RXD0- TXD1+ 110 PDO1 TXD1- PDI1 RXD1+ PCI1 100 RXD1- TXD2+ 110 PDO2 TXD2- PDI2 RXD2+ PCI2 100 RXD2- TXD3+ 110 TXD3- PDO3 PDI3 PCI3 RXD3+ 100 RXD3- REXT RST 13K CLK Typical Am79C983A TP Connector TP Connector TP Connector TP Connector AV DD 19879B-11 ...
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... RDI– DI– 40 RDO+ DO+ DO– RDO– RCI+ CI+ RCI– CI– – 150 + Normal Mode (with MAU) Am79C983A ML4663 TX+ TX– RX+ RX– COL+ COL– 19879B-12 Am79C983 RDI+ RDI– 40 RDO+ RDO– 0.1 F RCI+ RCI– 40 ...
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... PAUI drivers. The PAUI will operate reliably with a load up to 100 pF system that uses sockets for the IMR2 devices, the maximum number of devices is six. This number can in- crease as long as the total load capacitance is kept below 100 pF. Am79C983A COL JAM PCLK PDRV PDAT ...
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... PDI IMR2 1 PCI PDO PDI PCI Backplane 2 PDO PDI PCI PDO Am79C983 PDI PCI PDO PDI IMR2 2 PCI PDO PDI PCI Figure 11. Port Switching Configuration Am79C983A PDO TX PDI Port 0 PCI A RX PDO TX PDI m Port 1 PCI RX 7 PDO TX Port 2 PDI PCI RX ...
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... (Note (Note 1) V (Note MAX DD - MCLK = 20 MHz V = +5.25V DD MCLK = 20 MHz V = +5.25V DD Am79C983A ) . . . . . . . . . . . . . + Min Max Unit -0.5 0.8 V 2.0 0.5 0 0.4 V -500 500 -350 -160 ...
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... IN ASQ (Note 5) |V |>| ASQ (Note 6) (Note 1) (Note 1) (Note 1) |V |>| ASQ |V |>| ASQ |V |>| ASQ |V |>| ASQ C =100pF L C =100pF L Am79C983A Min Max Unit 49.995 50.005 0 ECLK ECLK 0 ECLK ECLK - ...
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... PDI pulses narrower than tPWOPDI (min) will be rejected; PDI pulses wider than tPWOPDI (max) will turn internal PDI carrier sense on Test Conditions C =100pF L C =100pF L C =100pF L C =100pF L C =100pF L C =100pF L Am79C983A Min Max Unit ...
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... PCI pulses narrower than tPWOPCI (min) will be rejected; PCI pulses wider than tPWOPCI (max) will turn internal PCI carrier sense on. 10. PCI pulses narrower than tPWKPCI (min) will maintain internal PCI carrier sense on; PCI pulses wider than tPWKPCI (max) will turn internal PCI carrier sense off. 11. Squelch thresholds change proportionately with Am79C983A 53 ...
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... Will be Change Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State tMCLK tMCLKH tMCLKL Figure 12. Master Clock (MCLK) Timing tECLK tECLKH tECLKL Am79C983A KS00010 19879B-16 19879B-17 ...
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... TCLK* REQ REQ ACK ACK COL COL DAT/JAM *TCLK illustrates internal IMR2 chip clock phrase relationships Figure 15. Expansion Bus Output Timing - Synchronous Mode tMDSET tMDHOLD IN tMHRH tMHRL tMASET tMAHLD tMHDZ tMHDR OUT Am79C983A 19879B-18 tMASET 19879B-19 55 ...
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... Figure 16. Expansion Port Collision Timing - Synchronous Mode PCLK PDAT PENAO ECLK REQ ACK COL DAT Figure 18. Expansion Port Input Timing - Asynchronous Mode tMHRH tMHRL tMASET tMAHLD tDPRV Figure 17. Packet Report Port Timing tEDSET tEDHOLD IN Am79C983A tMASET 19879B-20 19879B-21 19879B-22 ...
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... SWITCHING WAVEFORMS ECLK REQ ACK COL DAT Figure 19. Expansion Port Output Timing - Asynchronous Mode MCLK PDO tPDOTD PCI VASQ tPWKPCI tPWOPCI tELDR Figure 20. PAUI PDO Transmit tPWKPCI Figure 21. PAUI PCI Receive Am79C983A 19879B-23 19879B-24 19879B-25 57 ...
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... SWITCHING WAVEFORMS PDI VASQ tPWKPDI tPWOPDI MCLK tDOTD DO+ DO– RDI VASQ tPWKDI tPWODI tPWKPDI Figure 22. PAUI Receive tDOETD tDOTR tDOTF Figure 23. (R)AUI Timing tPWKDI Figure 24. (R)AUI Receive Am79C983A 19879B-26 19879B-27 19879B-28 ...
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... SWITCHING WAVEFORMS C/D CS RD, WR RDY D7–0 D7–0 Figure 25. Microprocessor Bus Interface Timing tCDS tCSS tCSH tRDYD tRDYH tDOUT Read Data tDIS Write Data Am79C983A tCDH tREST tREST tDOH tDIH 19879B-29 59 ...
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... Pin 66 0.008 0.012 TOP VIEW 0.025 BASIC 0.80 REF 0.020 0.040 BOTTOM VIEW Characteristics tables. Also, the Table of Contents has been moved to page 7. No other technical changes have been made. Am79C983A Pin 99 0.947 0.953 1.075 1.085 1.097 1.103 0.130 0.150 0.160 0.180 ...