SLA4028 Seiko Epson Corp, SLA4028 Datasheet

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SLA4028

Manufacturer Part Number
SLA4028
Description
High Density Gate Array
Manufacturer
Seiko Epson Corp
Datasheet

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Manufacturer
Quantity
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Part Number:
SLA4028F2T
Manufacturer:
SEIKO/精工
Quantity:
20 000
Part Number:
SLA4028F4Y
Manufacturer:
CY
Quantity:
12 388
Part Number:
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VIA
Quantity:
1 831
The SLA 40000 series are super-high-density/speed, Sea-of-gate type CMOS gate arrays adopting the 0.45É m
process.
They consume less electricity, a feature of ASICs dedicated to 3.3V, while enabling high-speed-operation as well
as 3V/5V full swing I/F in the level shifter.
There are 2- and 3-metal layer for each of 8 models from 28,260 to 411,257 gates, satisfying customer needs for
a wide range of circuit size.
In addition, the series can be used with various I/F devices such as low noise output cells, PCI I/F revision 2.0, GTL
I/F*, JTAG*, fail/safe output* and test control input*, and have diverse applications such as small information
instrument and for image processing.
To develop high-speed/high-density circuits in a shorter period of time, the series enable diverse design techniques
to be used during development such as high accuracy simulation of interconnection resistance and blunted
waveform in addition to the conventional interconnection capacity components, and provide a new layout tool for
reducing clock skew.
OVERVIEW
FEATURES
PRODUCT LINEUP
Features
Total BCs (Raw Gates)
Usable BCs
Number of PADs
(In Case of Micro Pitch)
Propagation
Delay
I/O Level
Input Mode
Output Mode
Super-high density (adopting 0.45 m silicon gate CMOS with 2- and 3-metal layers)
High-speed operation (operation delay of internal gate = 0.160ns at 3.3V, 2-input power NAND standard)
Internal gate = 3.3 and 3.0V (2.0V single), I/O buffer = 5.0, 3.3 and 3.0V (2.0V single) (built-in level shifter)
Low power consumption (0.80 W/MHz/BC when internal cell = 3.0V)
Output drivability (I
RAM, PLL, IrDA*, and various function cells available
Low noise output cell, PCI I/F, USB I/F*, LVDS*, JTAG
Master
Output Buffers
Internal Gates
I
Input Gates
OL
OL
2-layer Metal
3-layer Metal
2-layer Metal
3-layer Metal
= 100 , 1, 3, 6, 12, 24 mA when PCI = 5.0V, I
= 50 , 300 , 600 , 2, 4mA when 2.0V)
LVTTL, TTL, CMOS, Pull-up/Pull-down, Schmitt, 2.0/3.0/3.3/5.0V Level interface (Level shifter)
SLA402T
SLA4028
28,260
14,130
24,868
(128)
Normal, Open drain, 3-state, Bi-directional, 2.0/3.0/3.3/5.0V Level interface (Level shifter)
116
tpd = 1.99ns (standard at 5.0V) level shifter, tpd = 1.89ns (standard at 3.3V) CL = 50pF
tpd = 0.400ns (standard at 5.0V) level shifter, tpd = 0.420ns (standard at 3.3V)
SLA404T
SLA4046
46,864
22,026
39,834
SLA40000 Series
(164)
144
High Density Gate Array
SLA407T
SLA4078
78,600
35,370
62,880
(212)
184
CMOS, TTL, PCI, USB*, LVDS*
tpd = 0.160ns (standard at 3.3V)
Super-high-density/speed gate array
Operates on 3.3 and 3.0V power source
(level shifter is pre-installed)
Raw of gates: 28 to 411k gates
(sea of gates)
SLA4115
SLA411T
115,388
51,924
86,541
(256)
216
OL
= 100 , 1, 2, 6, 12mA when PCI = 3.3V,
SLA4162
SLA416T
162,864
122,148
70,031
(304)
256
SLA4239
SLA423T
239,468
167,627
95,787
(368)
308
SLA4318
SLA431T
318,308
127,323
222,815
* Under development
(424)
352
PF842-02
SLA4411
SLA441T
411,257
164,502
287,879
(480)
400
1

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SLA4028 Summary of contents

Page 1

... 300 , 600 , 2, 4mA when 2.0V) OL RAM, PLL, IrDA*, and various function cells available Low noise output cell, PCI I/F, USB I/F*, LVDS*, JTAG PRODUCT LINEUP 2-layer Metal SLA4028 Master Features 3-layer Metal SLA402T Total BCs (Raw Gates) Usable BCs 2-layer Metal 3-layer Metal ...

Page 2

... Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. All product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ©Seiko Epson Corporation 1998 All rights reserved. ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing & ...

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