W49V002 Winbond, W49V002 Datasheet - Page 24

• Manufacturer Part Number: W49V002
• Description: 256K X 8 CMOS FLASH MEMORY WITH FWH INTERFACE
• Manufacturer: Winbond

Timing Waveforms for LPC Interface Mode, continued
#DATA Polling Timing Diagram
LAD[3:0]
LAD[3:0]
LAD[3:0]
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
#RESET
#LFRAM
#RESET
#LFRAM
#RESET
#LFRAM
CLK
CLK
CLK
1 Clock
1 Clock
1 Clock
1st Start
0000b
0000b
Start
0000b
Start
1 Clock
1 Clock
1 Clock
Memory
Write
Cycle
011Xb
Memory
Read
Cycle
010Xb
Memory
Read
Cycle
010Xb
An[31:28] An[27:24]
An[31:28] An[27:24]
An[31:28] An[27:24]
Write the last command(program or erase) to the device in LPC mode.
An[23:20] An[19:16]
An[23:20] An[19:16]
An[23:20] An[19:16]
Load Address "An" in 8 Clocks
Load Address in 8 Clocks
Load Address in 8 Clocks
Read the DQ7 to see if the internal write complete or not.
When internal write complete, the DQ7 will equal to Dn7.
Address
Address
Address
An[15:12]
An[15:12]
An[15:12] An[11:8]
XXXXb
- 24 -
An[11:8]
An[11:8]
An[7:4]
An[7:4]
An[7:4]
An[3:0]
An[3:0]
An[3:0]
Preliminary W49V002A
Dn[3:0]
Load Data "Dn"
1111b
in 2 Clocks
1111b
2 Clocks
2 Clocks
Data
TAR
TAR
Dn[7:4]
Tri-State 0000b
Tri-State 0000b
1 Clock
1 Clock
1111b
Sync
Sync
2 Clocks
TAR
Tri-State
Data out 2 Clocks
Data out 2 Clocks
XXXXb
XXXXb
Data
Data
1 Clock
Dn7,xxx
Dn7,xxx
0000b
Sync
TAR
TAR
TAR
Start next
command
1 Clock
Next Start
1 Clock
Next Start
1 Clock
0000b
0000b
0000b