AM29LV004B-150EEB AMD [Advanced Micro Devices], AM29LV004B-150EEB Datasheet
AM29LV004B-150EEB
Related parts for AM29LV004B-150EEB
AM29LV004B-150EEB Summary of contents
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PRELIMINARY Am29LV004 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications — Regulated voltage range: ...
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GENERAL DESCRIPTION The Am29LV004 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes. The device is offered in a 40-pin TSOP package. The byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt ...
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PRODUCT SELECTOR GUIDE Family Part Number Regulated Voltage Range: V Speed Options Full Voltage Range: V Max access time ACC Max CE# access time Max OE# access time Note: ...
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CONNECTION DIAGRAMS A16 1 A15 2 A14 3 A13 4 A12 5 A11 WE# 9 RESET RY/BY# 12 A18 ...
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PIN CONFIGURATION A0–A18 = 19 addresses DQ0–DQ7 = 8 data inputs/outputs CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output V = 3.0 volt-only single power ...
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... Valid Combinations Am29LV004T-70R, EC, EI, FC, FI Am29LV004B-70R Am29LV004T-80, Am29LV004B-80 Am29LV004T-90, EC, EI, EE, FC, FI, FE Am29LV004B-90 Am29LV004T-120, Am29LV004B-120 OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information) TEMPERATURE RANGE C = Commercial (0°C to +70° Industrial (– ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches ...
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Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, ...
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... SA3 0 1 SA4 1 0 SA5 1 0 SA6 1 1 SA7 1 1 SA8 1 1 SA9 1 1 SA10 1 1 Table 3. Am29LV004B Bottom Boot Block Sector Address Table Sector A18 A17 A16 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 0 SA5 0 1 SA6 ...
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... Table 4. Am29LV004 Autoselect Codes (High Voltage Method) Description Manufacturer ID: AMD Device ID: Am29LV004T (Top Boot Block) Device ID: Am29LV004B (Bottom Boot Block) Sector Protection Verification L = Logic Low = Logic High = V IL Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hard- ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 5 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or ...
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Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 shows the address and data requirements. This method is an alternative ...
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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip ...
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After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command ...
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Table 5. Am29LV004 Command Definitions Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Manufacturer ID Device ID, Top Boot Block Auto- select Device ID, Bottom Boot Block 4 (Note 7) Sector Protect Verify (Note 8) Program Chip Erase ...
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WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the following subsections de- scribe the functions of these bits. DQ7, RY/BY#, and ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, de- termining the ...
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Operation Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Reading within Erase Suspended Sector Erase Suspend Reading within Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . – +150 C Ambient Temperature with Power Applied . . . . . . . . ...
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DC CHARACTERISTICS CMOS Compatible Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Note 1) V Active Write Current CC I CC2 (Notes 2 ...
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DC CHARACTERISTICS (Continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 8. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C L 6.2 k Note: Diodes are IN3064 or equivalent Figure 10. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V Input 1.5 V 0.0 V Figure 11. Input Waveforms ...
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AC CHARACTERISTICS Read Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write (See Note) t RESET# ...
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AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# t GHWL OE Data RY/BY VCS Note program address program data ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE# t GHWL OE WE Data 55h RY/BY# t VCS V CC Note sector address (for Sector Erase ...
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AC CHARACTERISTICS t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...
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AC CHARACTERISTICS Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Temporary Sector ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH DS ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes Program Address Program Data, DQ7# = complement of the data written ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time (Note 3) Notes: 1. Typical program and erase times assume the following conditions 3 programming typicals assume checkerboard pattern. ...
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PHYSICAL DIMENSIONS* TS 040—40-Pin Standard TSOP (measured in millimeters) Pin 1 I. 18.30 18.50 19.80 20.20 1.20 MAX * For reference only. BSC is an ANSI standard for Basic Space Centering ...
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PHYSICAL DIMENSIONS TSR048—48-Pin Reverse TSOP (measured in millimeters) Pin 1 I. 18.30 18.50 19.80 20.20 1.20 MAX 9.90 10.10 21 0.08 0.20 0.10 0.21 0˚ 5˚ ...
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REVISION SUMMARY Global Revised formatting to be consistent with other current 3.0 volt-only data sheets. Revision D+1 AC Characteristics Erase/Program Operations; Alternate CE# Controlled Erase/Program Operations: Corrected the notes refer- Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights ...