NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 120

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
5.5.1.3
Cycle Type / Direction (CYCTYPE + DIR)
The ICH7 drives bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0.
Table 5-7
Table 5-7.
Cycle Type Bit Definitions
Bits[3:2]
Bit1
00
0
00
1
10
0
10
1
11
x
NOTE: All other encodings are RESERVED.
5.5.1.4
SIZE
Bits[3:2] are reserved. The ICH7 drives them to 00. Peripherals running bus master
cycles are also supposed to drive 00 for bits 3:2; however, the ICH7 ignores those bits.
Bits[1:0] are encoded as listed in
Table 5-8.
Transfer Size Bit Definition
Bits[1:0]
00
8-bit transfer (1 byte)
01
16-bit transfer (2 bytes)
Reserved. The Intel
10
running a bus master cycle drives this combination, the ICH7 may abort the
transfer.
11
32-bit transfer (4 bytes)
120
shows the valid bit encodings.
Definition
I/O Read
I/O Write
Desktop and Mobile: DMA Read
Ultra Mobile: Reserved
Desktop and Mobile: DMA Write
Ultra Mobile: Reserved
Reserved. If a peripheral performing a bus master cycle generates this
®
value, the Intel
ICH7 aborts the cycle.
Table
5-8.
Size
®
ICH7 does not drive this combination. If a peripheral
Functional Description
®
Intel
ICH7 Family Datasheet

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