NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 140

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
5.10
Advanced Programmable Interrupt Controller
(APIC) (D31:F0)
In addition to the standard ISA-compatible PIC described in the previous chapter, the
ICH7 incorporates the APIC. While the standard interrupt controller is intended for use
in a uni-processor system, APIC can be used in either a uni-processor or multi-
processor system.
5.10.1
Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these
differences are:
• Method of Interrupt Transmission. The I/O APIC transmits interrupts through
memory writes on the normal datapath to the processor, and interrupts are handled
without the need for the processor to run an interrupt acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the
interrupt number. For example, interrupt 10 can be given a higher priority than
interrupt 3.
• More Interrupts. The I/O APIC in the ICH7 supports a total of 24 interrupts.
• Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O
APIC devices in the system with their own interrupt vectors.
5.10.2
Interrupt Mapping
The I/O APIC within the ICH7 supports 24 APIC interrupts. Each interrupt has its own
unique vector assigned by software. The interrupt vectors are mapped as follows, and
match “Config 6” of the Multi-Processor Specification.
Table 5-16. APIC Interrupt Mapping (Sheet 1 of 2)
Via
1
IRQ #
SERIRQ
0
No
1
Yes
2
No
3
Yes
4
Yes
5
Yes
6
Yes
7
Yes
8
No
9
Yes
10
Yes
11
Yes
12
Yes
13
No
14
Yes
15
Yes
140
Direct
Via PCI
from Pin
Message
No
No
Cascade from 8259 #1
No
Yes
No
No
8254 Counter 0, HPET #0 (legacy mode)
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
No
RTC, HPET #1 (legacy mode)
No
Yes
Option for SCI, TCO
No
Yes
Option for SCI, TCO
No
Yes
HPET #2, Option for SCI, TCO
No
Yes
No
No
FERR# logic
IDEIRQ (legacy mode, non-combined or
3
Yes
Yes
combined mapped as primary), SATA Primary
(legacy mode)
IDEIRQ (legacy mode — combined, mapped as
Yes
Yes
secondary), SATA Secondary (legacy mode)
Functional Description
Internal Modules
2
®
Intel
ICH7 Family Datasheet

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