NH82801GBM SL8YB

Manufacturer Part NumberNH82801GBM SL8YB
ManufacturerIntel Corporation
NH82801GBM SL8YB datasheet
 

Specifications of NH82801GBM SL8YB

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Page 240/848

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®
5.23
Intel
High Definition Audio Overview
The ICH7’s Intel High Definition Audio controller shares pins with the AC ’97 controller.
However, only one controller may be enabled at a time.
Note:
The ICH7-U Ultra Mobile component does not contain an AC ‘97 controller.
The ICH7’s controller communicates with the external codec(s) over the Intel High
Definition Audio serial link. The controller consists of a set of DMA engines that are
used to move samples of digitally encoded data between system memory and an
external codec(s). The ICH7 implements four output DMA engines and 4 input DMA
engines. The output DMA engines move digital data from system memory to a D-A
converter in a codec. ICH7 implements a single Serial Data Output signal
(ACZ_SDOUT) that is connected to all external codecs. The input DMA engines move
digital data from the A-D converter in the codec to system memory. The ICH7
implements three Serial Digital Input signals (ACZ_SDI[2:0]) supporting up to three
codecs.
Audio software renders outbound and processes inbound data to/from buffers in
system memory. The location of individual buffers is described by a Buffer Descriptor
List (BDL) that is fetched and processed by the controller. The data in the buffers is
arranged in a predefined format. The output DMA engines fetch the digital data from
memory and reformat it based on the programmed sample rate, bit/sample and
number of channels. The data from the output DMA engines is then combined and
serially sent to the external codecs over the Intel High Definition Audio link. The input
DMA engines receive data from the codecs over the Intel High Definition Audio link and
format the data based on the programmable attributes for that stream. The data is
then written to memory in the predefined format for software to process. Each DMA
engine moves one stream of data. A single codec can accept or generate multiple
streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can
accept the same output stream processed by a single DMA engine.
Codec commands and responses are also transported to and from the codecs via DMA
engines.
®
5.23.1
Intel
High Definition Audio Docking (Mobile Only)
5.23.1.1
Dock Sequence
Note that this sequence is followed when the system is running and a docking event
occurs.
1. Since the ICH7 supports docking, the Docking Supported (DCKSTS. DS) bit defaults
to a 1. POST BIOS and ACPI BIOS software uses this bit to determine if the HD
Audio controller supports docking. BIOS may write a 0 to this RWO bit during POST
to effectively turn off the docking feature.
2. After reset in the undocked quiescent state, the Dock Attach (DCKCTL.DA) bit and
the Dock Mate (DCKSTS.DM) bit are both de-asserted. The AZ_DOCK_EN# signal is
de-asserted and AZ_DOCK_RST# is asserted. BCLK, SYNC and SDO signals may or
may not be running at the point in time that the docking event occurs.
3. The physical docking event is signaled to ACPI BIOS software via ACPI control
methods. This is normally accomplished through a GPIO signal on the ICH7 and is
outside the scope of this section.
4. ACPI BIOS software first checks that the docking is supported via DCKSTS.DS=1
and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1
to the DCKCTL.DA bit.
240
Functional Description
®
Intel
ICH7 Family Datasheet