MC56F8002VWL Freescale Semiconductor, MC56F8002VWL Datasheet
MC56F8002VWL
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MC56F8002VWL Summary of contents
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... Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2009-2011. All rights reserved. Document Number: MC56F8006 MC56F8006/MC56F8002 48-pin LQFP Case: 932-03 ...
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... Thermal Design Considerations . . . . . . . . . . . . . . . . . 67 9.2 Electrical Design Considerations 9.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10 Package Mechanical Outline Drawings . . . . . . . . . . . . . . . . . 70 10.1 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2 32-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.3 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Appendix A Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Appendix B Peripheral Register Memory Map and Reset Value . . . . . . . 80 Freescale Semiconductor ...
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... Power management controller (PMC) IEEE 1149.1 Joint Test Action Group (JTAG) interface Enhanced on-chip emulator (EOnCE) IEEE 1149.1 Joint Test Action Group (JTAG) interface 1 Some ADC inputs share the same pin. See MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor MC56F8006/MC56F8002 Family Configuration Table 1. 28-pin 6 9 ...
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... Digital Reg Analog Reg Low-Voltage PMC Supervisor Data ALU 36-Bit MAC Bit Three 16-bit Input Registers Manipulation Four 36-bit Accumulators Unit R/W Control System Bus Control PIT Power Management RTC Controller System ROSC Clock Integration Generator* OSC Module 2 Crystal Oscillator Freescale Semiconductor ...
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... One multi-function, six-output pulse width modulator (PWM) module — MHz PWM operating clock — 15 bits of resolution — Center-aligned and edge-aligned PWM signal mode — Phase shifting PWM pulse generation — Four programmable fault inputs with programmable digital filter MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Overview 5 ...
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... One serial communication interface (SCI) with LIN slave functionality — MHz operating clock — Full-duplex or single-wire operation — Programmable bit data format — Two receiver wakeup methods: – Idle line – Address mark — 1/16 bit-time noise detection MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... Phase lock loop (PLL) provides a high-speed clock to the core and peripherals — Provides 3x system clock to PWM and dual timer and SCI — Loss of lock interrupt — Loss of reference clock interrupt • Clock sources MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor 2 C) port Overview 7 ...
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... A full set of programmable peripherals — PWM, PGAs, ADCs, SCI, SPI, I various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as general-purpose input/outputs (GPIOs). MC56F8006/MC56F8002 Digital Signal Controller, Rev PIT, timers, and analog comparators — supports Freescale Semiconductor ...
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... LA Instruction LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Bit- Manipulation Unit Enhanced OnCE™ JTAG TAP MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Figure 2 and Figure 3. Figure 2 DSP56800E Core ALU1 Address Generation Unit Decoder (AGU) Interrupt M01 Unit N3 Looping Unit ...
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... GPIOA4 GPIOA3 Crystal GPIOA2 GPIOA1 GPIOA0 RESTE GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2 GPIOB1 GPIOB0 GPIOC7 GPIOC6 GPIOC5 GPIOC4 GPIOC3 GPIOC2 GPIOC1 GPIOC0 GPIOD3 GPIOD2 GPIOD1 GPIOD0 GPIOE7 GPIOE6 GPIOE5 GPIOE4 GPIOE3 GPIOE2 GPIOE1 GPIOE0 GPIOF3 GPIOF2 GPIOF1 GPIOF0 Freescale Semiconductor ...
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... Product Documentation The documents listed in Table 2 are required for a complete description and proper design with the 56F8006/56F8002. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table 2. 56F8006/56F8002 Device Documentation Topic DSP56800E Reference ...
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... Dual COMP PWM and JTAG Timer Ground CMP0_P2 CMP2_P3 CMP2_M3 T1 FAULT3 CMP0_P1 CMP0_M1 CMP0_P4 CMP1_M2 CMP1_P1 PWM2 V DDA V SSA CMP2_M1 CMP2_P4 CMP2_P1 CMP2_P2 CMP1_M1 FAULT0 CMP1_P2, TCK CMP2_OUT CMP1_OUT TIN3 PWM5 CMP0_OUT TIN2 FAULT0 T0 Freescale Semiconductor Misc. CLKIN RESET CLKO_1 CLKO_0 ...
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... CMP2_OUT 1 Shielded ADC input. 4.2 Pin Assignment MC56F8006 and MC56F8002 28-pin small outline IC (28SOIC) assignment is shown in low-profile quad flat pack (32LQFP) is shown in in Figure 6. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 4. 56F8006/56F8002 Pins (continued) 2 GPIO I C SCI SPI ADC PGA E6 ...
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... GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0 GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 Figure 4. Top View, MC56F8006/MC56F8002 28-Pin SOIC Package MC56F8006/MC56F8002 Digital Signal Controller, Rev DDA SSA ANB8 & PGA1+ & CMP0_M2/GPIOC4 GPIOB1/SS/SDA/ANA12 & CMP2_P3 GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN TDO/GPIOD1/ANB10/T0/CMP2_OUT TMS/GPIOD3/ANB11/T1/CMP1_OUT TDI/GPIOD0/ANB12/SS/TIN2/CMP0_OUT GPIOA0/PWM0 GPIOA1/PWM1 GPIOF0/XTAL GPIOA3/PWM3/TXD/EXTAL GPIOA4/PWM4/SDA/FAULT1/TIN2 GPIOB0/SCLK/SCL/ANB13/PWM3/T1 Freescale Semiconductor ...
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... GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN GPIOB1/SS/SDA/ANA12 & CMP2_P3 GPIOB7/TXD/SCL/ANA11 & CMP2_M3 GPIOB5/T1/FAULT3/SCLK ANB8 and PGA1+ & CMP0_M2/GPIOC4 ANB6 and PGA1– & CMP0_P4/GPIOC5 ANB4 & CMP1_P1/GPIOC6/PWM2 V DDA Figure 5. Top View, MC56F8006 32-Pin LQFP Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor ORIENTATION MARK ...
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... CLKIN or XTAL is selected as device external clock input, the CLK_MOD bit in the OCCS oscillator control register (OSCTL) needs to be set too. EXT_SEL bit in OSCTL selects CLKIN or XTAL. MC56F8006/MC56F8002 Digital Signal Controller, Rev Orientation Mark GPIOA3/PWM3/TXD/EXTAL GPIOA2/PWM2 GPIOE7/CMP1_M3 GPIOA4/PWM4/SDA/FAULT1/TIN2 GPIOB0/SCLK/SCL/ANB13/PWM3/ Vss GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 GPIOE6 GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0 GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1 GPIOB2/MISO/TIN2/ANA2 & ANB2/CMP0_OUT Freescale Semiconductor ...
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... GPIOA1 (PWM1) GPIOA2 23 35 (PWM2) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Supply Supply I/O Power — This pin supplies 3.3 V power to the chip I/O interface. Supply Supply I/O Ground — These pins provide ground for chip I/O interface. ...
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... EXT_SYNC — When not being used as a fault input, this pin can be used to receive a pulse to reset the PWM counter or to generate a positive pulse at the start of every PWM cycle. Input TIN3 — Dual timer module channel 3 input After reset, the default state is GPIOA5. Signal Description C serial data line. Freescale Semiconductor ...
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... Input/Open (TXD) (CLKO_1) GPIOB0 (SCLK) (SCL) Input/Open (ANB13) (PWM3) (T1) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Input enabled FAULT0 — PWM fault input 0 used for disabling selected PWM outputs in cases where fault conditions originate off-chip ...
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... ANA2 and ANB2 — Analog input to channel 2 of ADCA and ADCB. Input CMP0_OUT— Analog comparator 0 output. Output When used as an analog input, the signal goes to the ANA2 and ANB2. After reset, the default state is GPIOB2. Signal Description C serial data line. Freescale Semiconductor ...
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... OUT GPIOB4 (T0) (CLKO_0) (MISO) (SDA) Input/Open (RXD) (ANA0 and ANB0) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Input/ enabled MOSI — Master out/slave in. In master mode, this pin serves as the Output data output ...
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... ANA11 and CMP2_M3 — Analog input to channel 11 of ADCA and Input negative input 3 of analog comparator 2. When used as an analog input, the signal goes to the ANA11 and CMP2_M3. After reset, the default state is GPIOB7. Signal Description C serial data line. Freescale Semiconductor ...
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... ANA9 and PGA0– and CMP2_P4 (GPIOC2) GPIOC3 46 (EXT_ TRIGGER) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Analog Analog ANA5 and CMP1_M1— Analog input to channel 5 of ADCA and Input Input negative input 1 of analog comparator 1. Analog Port C GPIO — ...
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... Port C GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup enabled Analog ANB5 and CMP1_M2 — Analog input to channel 5 of ADCB and Input negative input 2 of analog comparator 1. After reset, the default state is GPIOC7. Signal Description Freescale Semiconductor ...
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... TCK (GPIOD2) (ANA4 and CMP1_P2) (CMP2_ OUT) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Input Input, Test Data Input — This input pin provides a serial input data stream internal to the JTAG/EOnCE port sampled on the rising edge of TCK pullup and has an on-chip pullup resistor ...
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... Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Analog enabled ANA6 and CMP2_P2 — Analog input to channel 6 of ADCA and Input positive input 2 of analog comparator 2. After reset, the default state is GPIOE4. Signal Description Freescale Semiconductor ...
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... GPIOF1 40 (CMP1_P3) GPIOF2 41 (CMP0_M3) GPIOF3 42 (CMP0_P3) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor State Type During Reset Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Analog enabled ANA8 and CMP2_P1— Analog input to channel 8 of ADCA and Input positive input 1 of analog comparator 2 ...
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... Reset Memory Allocation RESERVED 2 On-Chip RAM : 2 KB RESERVED • Internal program flash • Interrupt vector table locates from 0x00 0000 to 0x00 0065 • COP reset address = 0x00 0002 • Boot location = 0x00 0000 Use Restrictions Figure 7. Freescale Semiconductor ...
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... X:0x00 03FF X:0x00 0000 1 All addresses are 16-bit word addresses. 2 This RAM is shared with Program space starting at P: 0x00 8000. See Figure 8. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor 1 for 56F8002 at Reset (continued) Memory Allocation RESERVED 2 On-Chip RAM : 2 KB RESERVED • Internal program flash • ...
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... Dual Port RAM Figure 8. 56F8002 Dual Port RAM Map Data EOnCE 0xFF FF00 Reserved 0x01 0000 Peripherals 0x00 F000 Reserved 0x00 0400 RAM 0x00 0000 Data EOnCE 0xFF FF00 Reserved 0x01 0000 Peripherals 0x00 F000 Reserved 0x00 0400 RAM 0x00 0000 Freescale Semiconductor ...
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... System Integration Module Power Management Controller Analog Comparator 0 Analog Comparator 1 Analog Comparator 2 Programmable Interval Timer Programmable Delay Block Real Timer Clock Flash Memory Interface MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Prefix TMR PWM INTC ADCA ADCB PGA0 PGA1 SCI SPI ...
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... Register Name Transmit Register Upper Word Receive Register Upper Word Transmit Register Receive Register Reserved Control Register Instruction Step Counter Status Register Trace Buffer Control Register Trace Buffer Pointer Register Trace Buffer Register Stages Reserved Reserved Reserved Reserved Reserved Freescale Semiconductor ...
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... Ability to put the internal relaxation oscillator into standby mode • Ability to power down the PLL MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor and V are also the voltage reference high and voltage reference low inputs, SSA General System Control Information and V ...
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... In the other oscillator modes, load capacitors ( and feedback resistor (R ) are required. In addition, a series resistor ( Recommended component values are listed in MC56F8006/MC56F8002 Digital Signal Controller, Rev may be used in high-gain modes. S Table 27. Figure 9, Figure 10, and Freescale Semiconductor ...
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... XTAL and the EXTAL pin is grounded or configured as GPIO while CLK_MOD bit in OSCTL register is set. The external clock input must be generated using a relatively low impedance driver with maximum frequency less than 8 MHz. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor General System Control Information 56F8002/56F8006 ...
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... Core and peripheral clock control and distribution • Stop/wait mode control • System status control MC56F8006/MC56F8002 Digital Signal Controller, Rev 56F8006/56F8002 XTAL EXTAL External Clock GND or GPIO (<50 MHz) Figure 13. The external clock source is connected 56F8002/56F8006 GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN External Clock ( 64 MHz) Freescale Semiconductor ...
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... CMP1 Trigger0 Trigger1 System Clock SSEL[1] SSEL[0] ADCA ADCA Trigger ADHWT ANA15 ANA7 ANA9 MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor CMP2 PWM EXT Trigger2 Trigger3 Trigger4 Programmable Delay Block (PDB) Pre- Pre- TriggerA TriggerB TriggerA TriggerB PGA0 Controller PGA1 Controller Figure 14 ...
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... After flash security is set, an authorized user can be enabled to access on-chip memory if a user-defined software subroutine, which reads and transfers the contents of internal memory via peripherals, is included in the application software. This MC56F8006/MC56F8002 Digital Signal Controller, Rev NOTE Freescale Semiconductor ...
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... Debug menu. This lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor NOTE Security Features 39 ...
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... MC56F8006/MC56F8002 Digital Signal Controller, Rev NOTE Unit.” The customer would need to supply technical support are stress ratings only, and functional operation at the maximum is not guaranteed. Stress = SSA DD DDA CAUTION = 3.0–3 < MHz OP Freescale Semiconductor ...
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... All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM), and the charge device model (CDM). MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 12. Absolute Maximum Ratings ( ...
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... Four layer board R (2s2p) Single layer board R (1s) Value Unit 1500 100 200 pF 3 –2.5 V 7.5 V Typ Max Unit — — V — — V — — into account in power calculations, determine I will be very small Value Unit (LQFP) 70 °C °C/W JMA 55 °C/W JMA Freescale Semiconductor ...
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... Junction to board Junction to case Junction to package top Junction-to-ambient thermal resistance determined per JEDEC JESD51–3 and JESD51–6. Thermal test board meets JEDEC specification for this package. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Comments Symbol Four layer board R JMA (2s2p) ...
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... 85°C avg FLRET Min Typ Max 3 3.3 3.6 –0.1 0 0.1 –0 –0.3 0.8 2 0.3 DDA –0.3 0.8 — –4 — –8 — 4 — 8 –40 105 10,000 — 15 — 20 — — Freescale Semiconductor Unit MHz °C cycles years years ...
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... Input leakage all input only pins current Hi-Z (off-state) all input/output leakage current MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 19. Default Mode Pin Group 1 GPIO, TDI, TDO, TMS, TCK Pin Group 2 SCL, SDA ADC and Comparator Pin Group 3 ...
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... LVDL , the injection current may flow out load shunts current greater DD Freescale Semiconductor Unit ...
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... Figure 16. Typical Low-Side Driver (Sink) Characteristics — Low Drive (GPIO_x_DRIVEn = 0) TYPICAL 0.8 –40 C 0.6 0.4 0 (mA) OL Figure 17. Typical Low-Side Driver (Sink) Characteristics — High Drive (GPIO_x_DRIVEn = 1) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor – 3.2 3.4 3 0.2 0.15 0.1 ...
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... Figure 19. Typical High-Side (Source) Characteristics — High Drive (GPIO_x_DRIVEn = 1) MC56F8006/MC56F8002 Digital Signal Controller, Rev 3 0.25 0.2 0.15 0.1 0.05 0 –15 – 3 0.2 0.1 0 –20 –25 –30 1 (mA) TYPICAL V – SPEC – (V) DD TYPICAL V – SPEC – – – (V) DD Freescale Semiconductor – ...
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... PLL engaged; all peripheral module and core clocks are off; ADC/DAC/comparator powered off; processor core in stop state MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 21. Supply Current Consumption Typical @ 3.3 V, 25°C Conditions I 41.52 mA 340.75 A 166 ...
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... Typical @ 3.3 V, 25°C Conditions I 194.69 A 2.77 A 879.72 nA 499.15 nA 494.04 nA Table 22. Flash Timing Parameters Symbol Min t prog 20 t erase 100 Maximum @ 3.6 V, 25° DDA DD 65.51 A 340 A 13. 11. 13 12. Typ Max Unit — 40 — — ms — — ms Freescale Semiconductor I DDA 120 A 3.0 A 2.4 A 2 ...
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... From powerdown to powerup state at 32 MHz system clock state. 5 This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 32 MHz system clock frequency and using an 8 MHz oscillator frequency. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Symbol Min 2 f ...
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... Figure 21. Relaxation Oscillator Temperature Variation (Typical) After Trim MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 25. Relaxation Oscillator Timing Symbol Minimum 1 f — — roscs t — jitterrosc 3 4 — 4 — Degrees C (Junction) Typical Maximum Unit — 8.05 MHz 400 kHz 400 — ps — –3.0 to +2.0 % — +2.0 to –2.0 % Freescale Semiconductor ...
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... At 4 MHz (used coming out of reset and stop modes 250 ns. 2 Parameters listed are guaranteed by design. GPIO pin (Input) Figure 22. GPIO Interrupt Timing (Negative Edge-Sensitive) 8.12 External Oscillator (XOSC) Characteristics Reference Figure 9, and Figure 10, and MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor NOTE Symbol Typical Min 96T + 64T RDA ...
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... TBD — CSTL — TBD — t — TBD — CSTH — TBD — f — — 50.0 xtal ) are incorporated internally when S High 90% 50% 10% Rise Time )/2. IL Freescale Semiconductor Unit MHz MHz MHz MHz Figure 23. ...
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... Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor and Data2 Valid Data2 Data Three-stated Figure 24. Signal States 1 Table 28 ...
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... Figure 25. SPI Master Timing (CPHA = 0) Max Unit See Figure Figure 25, 4.5 ns Figure 26, 20.4 ns Figure 27, Figure 28 Figure 25, — ns Figure 26, — ns Figure 27, Figure 28 Figure 25, 11.5 ns Figure 26, 10.0 ns Figure 27, Figure 28 Figure 25, 9.7 ns Figure 26, 9.0 ns Figure 27, Figure LSB in t (ref Master LSB out t R Freescale Semiconductor ...
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... SCLK (CPOL = 1) (Output) MISO (Input) t (ref) DV MOSI (Output) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor SS is held High on master MSB in Bits 14– Master MSB out Bits 14– Figure 26. SPI Master Timing (CPHA = 1) ...
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... LIN Slave Mode F –14 TOL_UNSYNCH F –2 TOL_SYNCH T 13 BREAK ELG Slave LSB out t DI LSB in Max Unit See Figure (f /16) Mbps MAX 1.04/BR ns Figure 29 1.04/BR ns Figure — Master node bit periods — Slave node bit periods Freescale Semiconductor — — — — — ...
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... SDA and SCL lines. 2 The maximum t must be met only if the device does not stretch the LOW period (t HD; DAT MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor RXD PW Figure 29. RXD Pulse Width TXD PW Figure 30 ...
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... SU; STA SR t HIGH Table 31. JTAG Timing Symbol Min Max f DC SYS_CLK — — Figure 32. Test Clock Input Timing Diagram HD; STA SP t SU; STO Bus Unit See Figure MHz Figure 32 — ns Figure 32 — ns Figure 33 — ns Figure Figure Figure Freescale Semiconductor t BUF S ...
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... Timer input high/low period Timer output period Timer output high/low period 1 In the formulas listed the clock cycle. For 32 MHz operation 31.25ns. 2. Parameters listed are guaranteed by design. Timer Inputs Timer Outputs MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor t DS Input Data Valid Table 32 ...
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... LSB 1 + 1/2 LSB 2 – 1/2 LSB 2 + 1/2 LSB 4 – 1 LSB LSB 8 – 1 LSB LSB 16 – 4 LSB LSB 32 – 4 LSB LSB PGA sampling rate/2 PGA sampling rate/8 100 2000 –40 125 Freescale Semiconductor Unit Hz nA Unit V/V V/V MHz Hz kHz o C ...
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... REFL SSA REFH DDA – Figure 35. ADC Input Impedance Equivalency Diagram MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 35. ADC Operating Conditions Symb Min ADIN REFL C — ADIN R — ADIN R AS — — — — ) — ...
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... ADCK cycles — — ADCK cycles — 2 — LSB 0.5 1.0 0.3 0.5 2 1.5 — LSB 0.5 1.0 0.3 0.5 2 — LSB — 0.5 — 0 — LSB Pad leakage R AS 0.2 4 0.1 1.2 — mV/ C — — mV Freescale Semiconductor = 4 * ...
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... Section 8.6, “Supply Current Characteristics,” for a list of I provides additional detail that can be used to optimize power consumption for a given application. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor =1.0 MHz unless otherwise stated. Typical values are for ADCK Table 37. HSCMP Specifications ...
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... CMOS power dissipation corresponding to the 56800E core and 2 *F, although simulations on two of the I/O cell types used on the 56800E Intercept 8 mA drive 1 drive 1.15 mW Slope 0.11 mW/pF 0.11 mW/pF Freescale Semiconductor Eqn. 1 Eqn. 2 ...
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... The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about wire extending from the MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor , can be obtained from the equation: J ...
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... MC56F8006/MC56F8002 Digital Signal Controller, Rev CAUTION , V , and V REF DDA and V and separate ground planes for V DD DDA traces. SSA pin on the 56F8006/56F8002 and from the and V (GND) pins are DD SS pins. SSA and V are recommended. SS SSA 2 C, the designer should RC filter. Freescale Semiconductor pairs, SS and DD ...
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... MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Pin Frequency Package Type Count (LQFP) 48 (LQFP) Design Considerations Ambient Temperature Order Number (MHz) Range 32 –40° 105° C MC56F8002VWL 32 –40° 105° C MC56F8006VWL 32 –40° 105° C MC56F8006VLC 32 –40° 105° C MC56F8006VLF ...
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... Package Mechanical Outline Drawings 10 Package Mechanical Outline Drawings 10.1 28-pin SOIC Package MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Package Mechanical Outline Drawings 71 ...
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... Package Mechanical Outline Drawings Figure 36. 56F8006/56F8002 28-Pin SOIC Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Package Mechanical Outline Drawings 73 ...
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... Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... Figure 37. 56F8006/56F8002 32-Pin LQFP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Package Mechanical Outline Drawings 75 ...
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... Package Mechanical Outline Drawings 10.3 48-pin LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... Figure 38. 56F8006/56F8002 48-Pin LQFP Mechanical Information 11 Revision History Table 40 lists major changes between versions of the MC56F8006 document. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Revision History 77 ...
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... P:0x10 3 P:0x12 Description 1 Interrupt Function 2 Reserved for Reset Overlay Reserved for COP Reset Overlay Illegal Instruction HW Stack Overflow Misaligned Long Word Access EOnCE Step Counter EOnCE Breakpoint Unit EOnCE Trace Buffer EOnCE Transmit Register Empty EOnCE Receive Register Full Freescale Semiconductor ...
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... N/A core 42 N/A core 43 N/A SWILP 44 N/A USER1 45 N/A USER2 46 N/A MC56F8006/MC56F8002 Digital Signal Controller, Rev. 3 Freescale Semiconductor Table 41. Interrupt Vector Table Contents Priority Vector Base Level Address + 0 P:0x14 0 P:0x16 Phase-Locked Loop Loss of Locks and Loss of Clock 0 P:0x18 0 P:0x1A 0 P:0x1C 0 P:0x1E ...
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Table 41. Interrupt Vector Table Contents Vector User Peripheral Number Encoding USER3 47 N/A USER4 48 N/A USER5 49 N/A 3 USER6 50 N/A 1 Two words are allocated for each entry in the vector table. This does not allow ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) TMR0_ 04 0000 TMR0 HOLD TMR0_ 05 0000 TMR0 CNTR TMR0_ 06 0000 TMR0 CM CTRL TMR0_ 07 0000 TMR0 TCF SCTRL ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) TMR1_ 14 0000 TMR1 HOLD TMR1_ 15 0000 TMR1 CNTR TMR1_ 16 0000 TMR1 CM CTRL TMR1_ 17 0000 TMR1 TCF SCTRL ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) PWM_ 23 0000 PWM OUT PWM_ 24 0000 PWM 0 CNTR PWM_ 25 0000 PWM 0 CMOD PWM_ 26 0000 PWM VAL0 ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) PWM_ 30 0000 PWM 0 CNFG PWM_ 31 0000 PWM nBX CCTRL PWM_ 1 32 00-U PWM 0 PORT PWM_ 33 0000 ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) INTC_ 40 0000 INTC INT ICSR INTC_ 41 0000 INTC 0 VBA INTC_ 42 0000 INTC 0 IAR0 INTC_ 43 0000 INTC ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) 6D–6F — ADC0 Reserved ADC1_ 80 001F ADC1 0 ADCSC1A ADC1_ 81 0000 ADC1 0 ADCSC2 82–85 — ADC1 Reserved ADC1_ 86 ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) A4–BF — PGA0 Reserved PGA1_ C0 0000 PGA1 0 CNTL0 PGA1_ C1 0002 PGA1 0 CNTL1 PGA1_ C2 000E PGA1 0 CNTL2 ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) SPI_ 01 000F SPI WOM DSCTRL 02 0000 SPI SPI_DRCV R15 R14 03 0000 SPI SPI_DXMIT T15 T14 04–1F — SPI Reserved ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) 30–3F — I2C Reserved COP_ 40 0302 COP 0 CTRL COP_ 41 FFFF COP TOUT COP_ 42 FFFF COP CNTR 43–5F — ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) GPIOA_ 80 00FF GPIOA 0 PUR 81 0000 GPIOA GPIOA_DR 0 GPIOA_ 82 0000 GPIOA 0 DDR GPIOA_ 83 0080 GPIOA 0 ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) GPIOB_ A2 0000 GPIOB 0 DDR GPIOB_ A3 0080 GPIOB 0 PER A4 — GPIOB Reserved GPIOB_ A5 0000 GPIOB 0 IENR ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) C4 — GPIOC Reserved GPIOC_ C5 0000 GPIOC 0 IENR GPIOC_ C6 0000 GPIOC 0 IPOLR GPIOC_ C7 0000 GPIOC 0 IPR ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) GPIOD_ E6 0000 GPIOD 0 IPOLR GPIOD_ E7 0000 GPIOD 0 IPR GPIOD_ E8 0000 GPIOD 0 IESR E9 — GPIOD Reserved ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) GPIOE_ 07 0000 GPIOE 0 IPR GPIOE_ 08 0000 GPIOE 0 IESR 09 — GPIOE Reserved GPIOE_ 0A 0000 GPIOE 0 RAWDATA ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) 29 — GPIOF Reserved GPIOF_ 2A 0000 GPIOF 0 RAWDATA GPIOF_ 2B 0000 GPIOF 0 DRIVE 2C 00FF GPIOF GPIOF_IFE 0 GPIOF_ ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) 48 0000 SIM SIM_SDR 49 F000 SIM SIM_ISAL 4A 0000 SIM SIM_PROT 0 4B 0000 SIM SIM_GPSA 0 SIM_ 4C 0000 SIM ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) CMP0_ 81 0000 CMP0 0 CR1 CMP0_ 82 0000 CMP0 0 FPR CMP0_ 83 0000 CMP0 0 SCR 84–9F — CMP0 Reserved ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) E0 0000 PIT PIT_CTRL 0 E1 0000 PIT PIT_MOD E2 0000 PIT PIT_CNTR E3–FF — PIT Reserved 00 0000 PDB PDB_SCR PRESCALER ...
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Table 42. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 15 (Hex) (Hex -000 HFM FM_SECHI FM_ 04 0000 HFM 0 SECLO 06–0F — HFM Reserved 6 10 FFFF HFM FM_PROT 11 — HFM ...
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