NH82801GBM SL8YB

Manufacturer Part NumberNH82801GBM SL8YB
ManufacturerIntel Corporation
NH82801GBM SL8YB datasheet
 


Specifications of NH82801GBM SL8YB

CaseBGADate_code07+
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LPC Interface Bridge Registers (D31:F0)
10.8.3.18
SS_CNT— Intel SpeedStep
Control Register (Mobile/Ultra Mobile Only)
I/O Address:
PMBASE +50h
Default Value
01h
Lockable:
No
Power Well:
Core
Note:
Writes to this register will initiate an Intel SpeedStep technology transition that
involves a temporary transition to a C3-like state in which the STPCLK# signal will go
active. An Intel SpeedStep technology transition always occur on writes to the
SS_CNT register, even if the value written to SS_STATE is the same as the previous
value (after this “transition” the system would still be in the same Intel SpeedStep
technology state). If the SS_EN bit is 0, then writes to this register will have no effect
and reads will return 0.
Bit
7:1
Reserved
SS_STATE (Intel SpeedStep
read, it returns the last value written to this register. By convention, this will be the
current Intel SpeedStep technology state. Writes to this register causes a change to the
Intel SpeedStep technology state indicated by the value written to this bit. If the new
value for SS_STATE is the same as the previous value, then transition will still occur.
0
0 = High power state.
1 = Low power state
NOTE: This is only a convention because the transition is the same regardless of the
value written to this bit.
10.8.3.19
C3_RES— C3 Residency Register (Mobile/Ultra Mobile Only)
I/O Address:
PMBASE +54h
Default Value
00000000h
Lockable:
No
Power Well:
Core
The value in this field increments at the same rate as the Power Management Timer.
This field increments while STP_CPU# is active (i.e. the CPU is in a C3 or C4 state). This
field will roll over in the same way as the Power Management Timer, however the most
significant bit is NOT sticky.
Bit
31:24
Reserved
C3_RESIDENCY — RO. The value in this field increments at the same rate as the Power
Management Timer. If the C3_RESEDENCY_MODE bit is clear, this field automatically
resets to 0 at the point when the Lvl3 or Lvl4 read occurs. If the C3_RESIDENCY_MODE
bit is set, the register does not reset when the Lvl3 or Lvl4 read occurs. In either mode,
it increments while STP_CPU# is active (i.e., the processor is in a C3 or C4 state). This
field will roll over in the same way as the PM Timer, however the most significant bit is
23:0
NOT sticky.
Software is responsible for reading this field before performing the Lvl3/4 transition.
Software must also check for rollover if the maximum time in C3/C4 could be
exceeded.
NOTE: Hardware reset is the only reset of this counter field.
®
Intel
ICH7 Family Datasheet
®
Technology
Attribute:
R/W (special)
Size:
8-bit
Usage:
ACPI/Legacy
Description
®
technology State) — R/W (Special). When this bit is
Attribute:
R/W/RO
Size:
32-bit
Usage:
ACPI/Legacy
Description
455