NH82801GBM SL8YB

Manufacturer Part NumberNH82801GBM SL8YB
ManufacturerIntel Corporation
NH82801GBM SL8YB datasheet
 


Specifications of NH82801GBM SL8YB

CaseBGADate_code07+
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LPC Interface Bridge Registers (D31:F0)
10.10.3
GP_LVL—GPIO Level for Input or Output Register
Offset Address: GPIOBASE +0Ch
Default Value:
02FE0000h
Lockable:
No
Bit
GP_LVL[31:0]— R/W: If GPIO[n] is programmed to be an output (via the
corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] bit
can be updated by software to drive a high or low value on the output pin. 1 = high,
0 = low.
31:0
If GPIO[n] is programmed as an input, then the corresponding GP_LVL bit reflects the
state of the input signal (1 = high, 0 = low.) and writes will have no effect.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have
no effect. The value reported in this register is undefined when programmed as
native mode.
10.10.4
GPO_BLINK—GPO Blink Enable Register
Offset Address: GPIOBASE +18h
Default Value:
00040000h
Lockable:
No
Bit
GP_BLINK[31:0] — R/W. The setting of this bit has no effect if the corresponding
GPIO signal is programmed as an input.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will
blink at a rate of approximately once per second. The high and low times have
approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is
set.
31:0
The value of the corresponding GP_LVL bit remains unchanged during the blink
process, and does not effect the blink in any way. The GP_LVL bit is not altered
when programmed to blink. It will remain at its previous value.
These bits correspond to GPIO in the Resume well. These bits revert to the default
value based on RSMRST# or a write to the CF9h register (but not just on
PLTRST#).
NOTE: (Desktop Only) GPIO18 will blink by default immediately after reset. This signal could be
connected to an LED to indicate a failed boot (by programming BIOS to clear GP_BLINK18
after successful POST).
®
Intel
ICH7 Family Datasheet
Attribute:
R/W
Size:
32-bit
Power Well:
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
Attribute:
R/W
Size:
32-bit
Power Well:
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
465