NH82801GBM SL8YB

Manufacturer Part NumberNH82801GBM SL8YB
ManufacturerIntel Corporation
NH82801GBM SL8YB datasheet
 

Specifications of NH82801GBM SL8YB

CaseBGADate_code07+
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SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.45
BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)
Address Offset: E8h
Default Value:
00000000h
Bits
BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form
the contents of the third DWord of any BIST FIS initiated by the Intel
register is not port specific; its contents will be used for BIST FIS initiated on any port.
31:0
Although the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of
the BIST FIS is set to indicate “Far-End Transmit mode”, this register’s contents will be
transmitted as the BIST FIS 3rd DW regardless of whether or not the “T” bit is indicated
in the BFCS register (D31:F2:E0h).
12.2
Bus Master IDE I/O Registers (D31:F2)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BAR register,
located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O
space registers can be accessed as byte, word, or DWord quantities. Reading reserved
bits returns an indeterminate, inconsistent value, and writes to reserved bits have no
effect (but should not be attempted). These registers are only used for legacy
operation. Software must not use these registers when running AHCI. The description
of the I/O registers is shown in
Table 12-2. Bus Master IDE I/O Register Address Map
BAR+
Mnemonic
Offset
00
BMICP
01
—
02
BMISP
03
—
04–07
BMIDP
08
BMICS
09
—
0Ah
BMISS
0Bh
—
0Ch–
BMIDS
0Fh
10h
AIR
14h
AIDR
®
Intel
ICH7 Family Datasheet
EBh
Attribute:
–
Size:
Description
Table
12-2.
Register
Command Register Primary
Reserved
Bus Master IDE Status Register Primary
Reserved
Bus Master IDE Descriptor Table Pointer
Primary
Command Register Secondary
Reserved
Bus Master IDE Status Register Secondary
Reserved
Bus Master IDE Descriptor Table Pointer
Secondary
AHCI Index Register
AHCI Index Data Register
R/W
32 bits
®
ICH7. This
Default
Type
00h
R/W
—
RO
R/W, R/
00h
WC, RO
—
RO
xxxxxxxxh
R/W
00h
R/W
—
RO
R/W, R/
00h
WC, RO
—
RO
xxxxxxxxh
R/W
00000000
R/W, RO
h
xxxxxxxxh
R/W
519

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