NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 532
Manufacturer Part Number
Specifications of NH82801GBM SL8YB
PxFBU—Port [3:0] FIS Base Address Upper 32-Bits
Address Offset: Port 0: ABAR + 10Ch
Port 1: ABAR + 18Ch
Port 2: ABAR + 20Ch
Port 3: ABAR + 28Ch
FIS Base Address Upper (FBU) — R/W. Indicates the upper 32-bits for the received
FIS base for this port.
Note that these bits are not reset on a HBA reset.
PxIS—Port [3:0] Interrupt Status Register (D31:F2)
Address Offset: Port 0: ABAR + 110h
Port 1: ABAR + 190h (ICH7R and ICH7DH Only)
Port 2: ABAR + 210h
Port 3: ABAR + 290h (ICH7R and ICH7DH Only
Cold Port Detect Status (CPDS) — RO. Cold presence not supported.
Task File Error Status (TFES) — R/WC. This bit is set whenever the status register is
updated by the device and the error bit (PxTFD.bit 0) is set.
Host Bus Fatal Error Status (HBFS) — R/WC. Indicates that the Intel
encountered an error that it cannot recover from due to a bad software pointer. In PCI,
such an indication would be a target or master abort.
Host Bus Data Error Status (HBDS) — R/WC. Indicates that the ICH7 encountered a
data error (uncorrectable ECC / parity) when reading from or writing to system
Interface Fatal Error Status (IFS) — R/WC. Indicates that the ICH7 encountered an
error on the SATA interface which caused the transfer to stop.
Interface Non-fatal Error Status (INFS) — R/WC. Indicates that the ICH7
encountered an error on the SATA interface but was able to continue operation.
Overflow Status (OFS) — R/WC. Indicates that the ICH7 received more bytes from a
device than was specified in the PRD table for the command.
Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the ICH7 received
a FIS from a device whose Port Multiplier field did not match what was expected.
NOTE: Port Multiplier not supported by ICH7.
PhyRdy Change Status (PRCS) — RO. When set to one indicates the internal PhyRdy
signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the
other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is
Note that the internal PhyRdy signal also transitions when the port interface enters
partial or slumber power management states. Partial and slumber must be disabled
when Surprise Removal Notification is desired, otherwise the power management state
transitions will appear as false insertion and removal events.
SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
ICH7 Family Datasheet