X4043 INTERSIL [Intersil Corporation], X4043 Datasheet
X4043
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X4043 Summary of contents
Page 1
... Reset logic September 30, 2005 DESCRIPTION The X4043/45 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space require- ments, and increases reliability. ...
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... X4045M8I-4.5A X4043M8IZ-4.5A (Note) DAU X4045M8IZ-4.5A (Note) DBE X4043P-4.5A X4043P AL X4045PZ-4.5A (Note) X4043PZ-4.5A (Note) X4043P Z AL X4045P-4.5A X4043PI-4.5A X4043P AM X4045PI-4.5A X4043PIZ-4.5A (Note) X4043P Z AM X4045PIZ-4.5A (Note) X4043S8* X4043 X4045S8* X4043S8Z* (Note) X4043 Z X4045S8Z* (Note) X4043S8I* X4043 I X4045S8I X4043S8IZ* (Note) X4043 Z I X4045S8IZ (Note) ...
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... ADH X4045M8I-2.7 X4043M8IZ-2.7(Note) DAS X4045M8IZ-2.7 (Note) X4043P-2.7 X4043P F X4045P-2.7 X4043PZ-2.7 (Note) X4043P Z F X4045PZ-2.7 (Note) X4043PI-2.7 X4043P G X4045PI-2.7 X4043PIZ-2.7 (Note) X4043P Z G X4045PIZ-2.7 (Note) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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... RESET/RESET SDA 6 SCL X4043, X4045 PIN CONFIGURATION ™ Function No internal connections No internal connections Reset Output. RESET is an active LOW, open drain output which goes active whenever V falls below will remain active until V CC TRIP V for t ...
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... PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4043/45 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – ...
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... V (actual) to the original V TRIP This is your new V that should be applied to V TRIP and the whole sequence should be repeated again (see Figure 5). 6 X4043, X4045 C ASE Now if the V (desired), perform the reset sequence as described in the next section. The new (desired)). ...
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... Level Sequence (V TRIP SCL SDA A0h Figure 4. Sample V Reset Circuit TRIP 4.7K RESET V TRIP Adj. 7 X4043, X4045 > 3V 15-18V, WEL bit set 15-18V 03h Adjust Run X4043 ...
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... DONE The user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores WD1, WD0, BP2, BP1, and BP0. The X4043/45 will not acknowledge any data bytes written after the first byte is entered. Let: MDE = Maximum Desired Error ...
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... The state of the control register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The X4043/45 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation ...
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... If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device 10 X4043, X4045 transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this fam- ily operate as slaves in all applications. ...
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... Upon a correct compare, the device outputs an acknowledge on the SDA line. Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power-up condition. Slave Address Byte Figure 9. X4043/45 Addressing Slave Byte Array Control Reg ...
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... As with the byte write opera- tion, all inputs are disabled until completion of the inter- nal write cycle. See Figure 11 for the address, acknowledge, and data transfer sequence. 12 X4043, X4045 S t Slave Byte a ...
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... Figure 14. Current Address Read Sequence Signals from the Master SDA Bus Signals from the Slave 13 X4043, X4045 Figure 13. Acknowledge Polling Sequence Byte Load Completed by Issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) ...
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... C Signals from K the Slave 14 X4043, X4045 of the word address bytes, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition ...
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... Communication to the device is inhibited as a result of a low voltage condition (V CC progress communication is terminated. – Block lock bits can protect sections of the memory array from write operations. 15 X4043, X4045 Symbol Table WAVEFORM < V )any in- TRIP INPUTS OUTPUTS ...
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... V max. are for reference only and are not tested X4043, X4045 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...
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... HD:WP Cb Capacitive load for each bus line Notes: (5) Typical values are for T = 25°C and total capacitance of one bus line in pF. 17 X4043, X4045 = 5V) CC Parameter A.C. TEST CONDITIONS Input pulse levels 5V Input rise and fall times Input and output timing levels 4.6kΩ ...
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... the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. 18 X4043, X4045 t t HIGH LOW ...
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... R RESET (X4043) RESET (X4045) RESET Output Timing Symbol V Reset trip point voltage, X4043/45-4.5A TRIP Reset trip point voltage, X4043/45 Reset trip point voltage, X4043/45-2.7A Reset trip point voltage, X4043/45-2.7 t Power-up reset time out PURST ( detect to RESET/RESET RPD CC ( fall time ...
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... SCL SDA (4043) RESET Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIP (V TRIP t TSU WP t VPS SCL 0 SDA A0h Start 20 X4043, X4045 Start Clockin ( RSP < t WDO Start ) 01h* sets V TRIP 03h* resets V TRIP ...
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... Program Voltage Off time before next cycle VPO V Programming Voltage Set Voltage Range TRAN TRIP V V Set Voltage variation after programming (-40 to +85°C). tv TRIP t WP Program Voltage Setup time VPS 21 X4043, X4045 = 2.0-5.5V; Temperature = 25°C CC Description Min. Max. Unit 10 µs 10 µs 10 µs 10 µ ...
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... PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 22 X4043, X4045 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.004 (0.19) 0.010 (0.25) X 45° 0.0075 (0.19) 0.250" ...
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... PACKAGING INFORMATION 8-Lead Miniature Small Outline Gull Wing Package Type M 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.036 (0.91) 0.032 (0.81) 0.040 ± 0.002 (1.02 ± 0.05) 0.007 (0.18) 0.005 (0.13) 23 X4043, X4045 0.118 ± 0.002 (3.00 ± 0.05) 0.0256 (0.65) Typ. 0.118 ± 0.002 (3.00 ± 0.05) 0.030 (0.76) 0.0216 (0.55) 7° Typ. 0.008 (0.20) 0.004 (0.10) 0.150 (3.81) Ref. ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 X4043, X4045 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) ...