SMBus Controller Registers (D31:F3)
ICH7 Family Datasheet
PCISTS—PCI Status Register (SMBUS—D31:F3)
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
RID—Revision Identification Register (SMBUS—D31:F3)
Offset Address: 08h
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Parity error detected.
Signaled System Error (SSE) — R/WC.
0 = No system error detected.
1 = System error detected.
Received Master Abort (RMA) — RO. Hardwired to 0.
Received Target Abort (RTA) — RO. Hardwired to 0.
Signaled Target Abort (STA) — R/WC.
0 = Intel
1 = The function is targeted with a transaction that the ICH7 terminates with a target
DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for DEVSEL#
assertion for positive decode.
01 = Medium timing.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list
structures in this function
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is
independent from the state of the Interrupt Enable bit in the PCI Command register.
Revision ID — RO. Refer to the Intel
Update for the value of the Revision ID Register.
See bit description
ICH7 did Not terminate transaction for this function with a target abort.
I/O Controller Hub 7 (ICH7) Family Specification