NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 588

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
14.1.14
HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset: 40h
Default Value:
00h
Bit
7:3
Reserved
2
I
C_EN — R/W.
0 = SMBus behavior.
2
1 = The Intel
formatting of some commands.
SMB_SMI_EN — R/W.
0 = SMBus interrupts will not generate an SMI#.
1
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer
to
Section 5.21.4
be enabled.
SMBus Host Enable (HST_EN) — R/W.
0 = Disable the SMBus Host controller.
1 = Enable. The SMB Host controller interface is enabled to execute commands. The
0
INTREN bit (offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host
controller to interrupt or SMI#. Note that the SMB Host controller will not respond
to any new requests until all interrupt requests have been cleared.
14.2
SMBus I/O Registers
Table 14-2. SMBus I/O Register Address Map
SMB_BASE
Mnemonic
+ Offset
00h
02h
03h
04h
XMIT_SLVA
05h
06h
07h
HOST_BLOCK_DB
08h
09h
RCV_SLVA
0Ah–0Bh
SLV_DATA
0Ch
0Dh
0Eh
SMLINK_PIN_CTL
588
Attribute:
Size:
Description
®
ICH7 is enabled to communicate with I
(Interrupts / SMI#). This bit needs to be set for SMBALERT# to
Register Name
HST_STS
Host Status
HST_CNT
Host Control
HST_CMD
Host Command
Transmit Slave Address
HST_D0
Host Data 0
HST_D1
Host Data 1
Host Block Data Byte
PEC
Packet Error Check
Receive Slave Address
Receive Slave Data
AUX_STS
Auxiliary Status
AUX_CTL
Auxiliary Control
SMLink Pin Control (TCO
Compatible Mode)
SMBus Controller Registers (D31:F3)
R/W
8 bits
2
C devices. This will change the
Default
Type
R/WC, RO,
00h
R/WC
(special)
00h
R/W, WO
00h
R/W
00h
R/W
00h
R/W
00h
R/W
00h
R/W
00h
R/W
44h
R/W
0000h
RO
00h
R/WC, RO
00h
R/W
See
register
R/W, RO
description
®
Intel
ICH7 Family Datasheet

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