NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 592

no-image

NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!" string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!"
592
4:2
Bit
1
0
SMB_CMD — R/W. The bit encoding below indicates which command the ICH7 is to
perform. If enabled, the ICH7 will generate an interrupt or SMI# when the command
has completed If the value is for a non-supported or reserved command, the ICH7 will
set the device error (DEV_ERR) status bit (offset SMBASE + 00h, bit 2) and generate
an interrupt when the START bit is set. The ICH7 will perform no command, and will not
operate until DEV_ERR is cleared.
000 = Quick: The slave address and read/write value (bit 0) are stored in the
001 = Byte: This command uses the transmit slave address and command registers.
010 = Byte Data: This command uses the transmit slave address, command, and
011 = Word Data: This command uses the transmit slave address, command, DATA0
100 = Process Call: This command uses the transmit slave address, command,
101 = Block: This command uses the transmit slave address, command, DATA0
110 = I
111 = Block Process: This command uses the transmit slave address, command,
NOTE: E32B bit in the Auxiliary Control register must be set for this command to work.
KILL — R/W.
0 = Normal SMBus host controller functionality.
1 = Kills the current host transaction taking place, sets the FAILED status bit, and
INTREN — R/W.
0 = Disable.
1 = Enable the generation of an interrupt or SMI# upon the completion of the
asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to
allow the SMBus host controller to function normally.
command.
transmit slave address register.
Bit 0 of the slave address register determines if this is a read or write
command.
DATA0 registers. Bit 0 of the slave address register determines if this is a read
or write command. If it is a read, the DATA0 register will contain the read data.
and DATA1 registers. Bit 0 of the slave address register determines if this is a
read or write command. If it is a read, after the command completes, the
DATA0 and DATA1 registers will contain the read data.
DATA0 and DATA1 registers. Bit 0 of the slave address register determines if
this is a read or write command. After the command completes, the DATA0 and
DATA1 registers will contain the read data.
registers, and the Block Data Byte register. For block write, the count is stored
in the DATA0 register and indicates how many bytes of data will be transferred.
For block reads, the count is received and stored in the DATA0 register. Bit 0 of
the slave address register selects if this is a read or write command. For writes,
data is retrieved from the first n (where n is equal to the specified count)
addresses of the SRAM array. For reads, the data is stored in the Block Data
Byte register.
DATA1 registers, and the Block Data Byte register. The read data is stored in the
Block Data Byte register. The ICH7 continues reading data until the NAK is
received.
DATA0 and the Block Data Byte register. For block write, the count is stored in
the DATA0 register and indicates how many bytes of data will be transferred.
For block read, the count is received and stored in the DATA0 register. Bit 0 of
the slave address register always indicate a write command. For writes, data is
retrieved from the first m (where m is equal to the specified count) addresses of
the SRAM array. For reads, the data is stored in the Block Data Byte register.
2
C Read: This command uses the transmit slave address, command, DATA0,
Description
SMBus Controller Registers (D31:F3)
Intel
®
ICH7 Family Datasheet

Related parts for NH82801GBM SL8YB