NH82801GBM SL8YB Intel Corporation, NH82801GBM SL8YB Datasheet - Page 735

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NH82801GBM SL8YB

Manufacturer Part Number
NH82801GBM SL8YB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of NH82801GBM SL8YB

Case
BGA
Date_code
07+
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Intel® High Definition Audio Controller Registers (D27:F0)
19.2.7
19.2.8
Intel
®
ICH7 Family Datasheet
WAKEEN—Wake Enable Register
(Intel
Memory Address:HDBAR + 0Ch
Default Value:
STATESTS—State Change Status Register
(Intel
Memory Address:HDBAR + 0Eh
Default Value:
15:3
15:3
2:0
2:0
Bit
Bit
Reserved.
SDIN Wake Enable Flags — R/W. These bits control which SDI signal(s) may
generate a wake event. A 1b in the bit mask indicates that the associated SDIN signal is
enabled to generate a wake.
Bit 0 is used for SDI0
Bit 1 is used for SDI1
Bit 2 is used for SDI2
NOTE: These bits are in the resume well and only cleared on a power on reset.
Reserved.
SDIN State Change Status Flags — R/WC. Flag bits that indicate which SDI signal(s)
received a state change event. The bits are cleared by writing 1’s to them.
Bit 0 = SDI0
Bit 1 = SDI1
Bit 2 = SDI2
NOTE: These bits are in the resume well and only cleared on a power on reset.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
Software must not make assumptions about the reset state of these bits and
must set them appropriately.
Software must not make assumptions about the reset state of these bits and
must set them appropriately.
0000h
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
16 bits
R/WC
16 bits
735

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