K4T1G164QE-HCF7

Manufacturer Part NumberK4T1G164QE-HCF7
ManufacturerSamsung
K4T1G164QE-HCF7 datasheet
 

Specifications of K4T1G164QE-HCF7

Date_code10+  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Page 24/45

Download datasheet (2Mb)Embed
PrevNext
K4T1G044QE
K4T1G084QE
K4T1G164QE
15.0 Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing.
tXARDS is expected to be used for slow active power down exit timing.
2. AL = Additive Latency.
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min) have been satisfied.
4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.
5. Timings are specified with command/address input slew rate of 1.0 V/ns.
6. Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns.
7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in
differential strobe mode and a slew rate of 1.0 V/ns in single ended mode.
8. Data setup and hold time derating.
Table 1 - DDR2-400/533 tDS/tDH derating with differential data strobe
∆tDS, ∆tDH Derating Values of DDR2-400, DDR2-533 (ALL units in ‘ps’, the note applies to entire Table)
4.0 V/ns
3.0 V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
125
45
125
45
1.5
83
21
83
21
1.0
0
0
0
0
DQ
0.9
-
-
-11
-14
Siew
0.8
-
-
-
-
rate
0.7
-
-
-
-
V/ns
0.6
-
-
-
-
0.5
-
-
-
-
0.4
-
-
-
-
Table 2 - DDR2-667/800 tDS/tDH derating with differential data strobe
∆tDS, ∆tDH Derating Values for DDR2-667, DDR2-800 (ALL units in ‘ps’, the note applies to entire Table)
4.0 V/ns
3.0 V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
100
45
100
45
1.5
67
21
67
21
1.0
0
0
0
0
DQ
0.9
-
-
-5
-14
Slew
0.8
-
-
-
-
rate
0.7
-
-
-
-
V/ns
0.6
-
-
-
-
0.5
-
-
-
-
0.4
-
-
-
-
DQS,DQS Differential Slew Rate
2.0 V/ns
1.8 V/ns
1.6 V/ns
125
45
-
-
-
-
83
21
95
33
-
-
0
0
12
12
24
24
-11
-14
1
-2
13
10
-25
-31
-13
-19
-1
-7
-
-
-31
-42
-19
-30
-
-
-
-
-43
-59
-
-
-
-
-
-
-
-
-
-
-
-
DQS,DQS Differential Slew Rate
2.0 V/ns
1.8 V/ns
1.6 V/ns
100
45
-
-
-
-
67
21
79
33
-
-
0
0
12
12
24
24
-5
-14
7
-2
19
10
-13
-31
-1
-19
11
-7
-
-
-10
-42
2
-30
-
-
-
-
-10
-59
-
-
-
-
-
-
-
-
-
-
-
-
24 of 45
DDR2 SDRAM
1.4V/ns
1.2V/ns
1.0V/ns
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
22
-
-
-
-
11
5
23
17
-
-
-7
-18
5
-6
17
6
-31
-47
-19
-35
-7
-23
-74
-89
-62
-77
-50
-65
-
-
-127
-140
-115
-128
1.4V/ns
1.2V/ns
1.0V/ns
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
31
22
-
-
-
-
23
5
35
17
-
-
14
-18
26
-6
38
6
2
-47
14
-35
26
-23
-24
-89
-12
-77
0
-65
-
-
-52
-140
-40
-128
Rev. 1.1 December 2008
0.8V/ns
-
-
-
-
-
-
-
-
-
-
-
-
5
-11
-38
-53
-103
-116
0.8V/ns
-
-
-
-
-
-
-
-
-
-
-
-
38
-11
12
-53
-28
-116