KU80960CF33 Intel, KU80960CF33 Datasheet

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KU80960CF33

Manufacturer Part Number

KU80960CF33

Description

IC MPU I960CF 33MHZ 196-QFP

Manufacturer

Intel

Datasheet

1.KU80960CF33.pdf (70 pages)

Specifications of KU80960CF33

Rohs Status

RoHS non-compliant

Processor Type

i960

Features

CF suffix, 32-Bit with DMA, 4K Cache

Speed

33MHz

Voltage

5V

Mounting Type

Surface Mount

Package / Case

196-QFP

Other names

803114

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

KU80960CF33

Manufacturer:

Intel

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

KU80960CF33

Manufacturer:

INTEL

Quantity:

84

Current page: 1 of 70
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80960CF-40, -33, -25

32-Bit High-Performance Superscalar

Embedded Microprocessor

Product Features

Socket and Object Code Compatible with 80960CA

Two Instructions/Clock Sustained Execution

Four 71 Mbytes/s DMA Channels with Data Chaining

Demultiplexed 32-Bit Burst Bus with Pipelining

32-Bit Parallel Architecture

Fast Procedure Call/Return Model

On-Chip Register Cache

On-Chip Instruction Cache

High Bandwidth On-Chip Data RAM

Selectable Big or Little Endian Byte

Ordering

— Two Instructions/clock Execution

— Load/Store Architecture

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers

— Manipulates 64-Bit Bit Fields

— 11 Addressing Modes

— Full Parallel Fault Model

— Supervisor Protection Model

— Full Procedure Call in 4 Clocks

— Caches Registers on Call/Ret

— Minimum of 6 Frames Provided

— Up to 15 Programmable Frames

— 4 Kbyte Two-Way Set Associative

— 128-Bit Path to Instruction Sequencer

— Cache-Lock Modes

— Cache-Off Mode

— 1 Kbyte On-Chip Data RAM

— Sustains 128 bits per Clock Access

Four On-Chip DMA Channels

32-Bit Demultiplexed Burst Bus

High-Speed Interrupt Controller

On-Chip Data Cache

— 71 Mbytes/s Fly-by Transfers

— 40 Mbytes/s Two-Cycle Transfers

— Data Chaining

— Data Packing/Unpacking

— Programmable Priority Method

— 128-Bit Internal Data Paths to

— Burst Bus for DRAM Interfacing

— Address Pipelining Option

— Fully Programmable Wait States

— Supports 8-, 16- or 32-Bit Bus Widths

— Supports Unaligned Accesses

— Supervisor Protection Pin

— Up to 248 External Interrupts

— 32 Fully Programmable Priorities

— Multi-mode 8-Bit Interrupt Port

— Four Internal DMA Interrupts

— Separate, Non-maskable Interrupt Pin

— Context Switch in 625 ns Typical

— 1 Kbyte Direct-Mapped, Write Through

— 128 bits per Clock Access on Cache Hit

Registers

Order Number: 272886-002

Datasheet

September 2002

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