E28F320J5-120 Intel Corporation, E28F320J5-120 Datasheet

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E28F320J5-120

Manufacturer Part Number
E28F320J5-120
Description
Intel StrataFlash memory 32 Mbit. Access speed 120 ns
Manufacturer
Intel Corporation
Datasheet
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Capitalizing on two-bit-per-cell technology, Intel StrataFlash™ memory products provide 2X the bits in 1X the
space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are
the first to bring reliable, two-bit-per-cell storage technology to the flash market.
Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result,
Intel StrataFlash components are ideal for code or data applications where high density and low cost are
required. Examples include networking, telecommunications, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing 28F016SA/SV, 28F032SA, and Word-Wide FlashFile memory devices (28F160S5
and 28F320S5).
Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel’s 0.4 micron ETOX™ V process technology, Intel StrataFlash memory provides the
highest levels of quality and reliability.
January 1998
High-Density Symmetrically-Blocked
Architecture
5 V V
Configurable x8 or x16 I/O
120 ns Read Access Time (32 M)
150 ns Read Access Time (64 M)
Enhanced Data Protection Features
Industry-Standard Packaging
64 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
2.7 V I/O Capable
Absolute Protection with
V
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
µBGA* Package, SSOP and TSOP
Packages (32 M)
PEN
CC
INTEL StrataFlash™ MEMORY TECHNOLOGY
Operation
= GND
32 AND 64 MBIT
28F320J5 and 28F640J5
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Cross-Compatible Command Support
32-Byte Write Buffer
640,000 Total Erase Cycles (64 M)
320,000 Total Erase Cycles (32 M)
Automation Suspend Options
System Performance Enhancements
Intel StrataFlash™ Memory Flash
Technology
Intel Basic Command Set
Common Flash Interface
Scaleable Command Set
6 µs per Byte Effective
Programming Time
10,000 Erase Cycles per Block
Block Erase Suspend to Read
Block Erase Suspend to Program
STS Status Output
ADVANCE INFORMATION
Order Number: 290606-004

Related parts for E28F320J5-120

E28F320J5-120 Summary of contents

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E INTEL StrataFlash™ MEMORY TECHNOLOGY 32 AND 64 MBIT 28F320J5 and 28F640J5 n High-Density Symmetrically-Blocked Architecture 64 128-Kbyte Erase Blocks ( 128-Kbyte Erase Blocks ( Operation CC 2.7 V I/O Capable n Configurable ...

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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s website at http://www.intel.com COPYRIGHT © INTEL CORPORATION 1997, 1998 *Third-party brands and names are the property of their respective owners. CG-041493 2 ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 1.0 PRODUCT OVERVIEW ...................................5 2.0 PRINCIPLES OF OPERATION .....................11 2.1 Data Protection ..........................................12 3.0 BUS OPERATION .........................................12 3.1 Read ..........................................................13 3.2 Output Disable ...........................................13 3.3 Standby......................................................13 3.4 Reset/Power-Down ....................................13 3.5 Read ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT FIGURES Figure 1. Intel StrataFlash™ Memory Block Diagram..............................................6 Figure 2. µBGA* Package (64-Mbit and 32-Mbit)9 Figure 3. TSOP Lead Configuration (32-Mbit) ..10 Figure 4. SSOP Lead Configuration (64-Mbit and 32-Mbit) .....................................11 Figure ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 1.0 PRODUCT OVERVIEW The Intel StrataFlash™ memory family contains high-density memories organized as 8 Mbytes or 4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT are valid. Likewise, the device has a wake time (t ) from RP#-high until writes to the CUI are PHWL recognized. With RP# at GND, the WSM is reset and the status ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 1. Lead Descriptions Symbol Type A INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the device mode. This address is latched during a x8 ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 1. Lead Descriptions (Continued) Symbol Type BYTE# INPUT BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on DQ high and low byte. ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT GND PEN ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 28F016SV 28F160S5 28F032SA 28F320J5 28F016SA 3/5# 3/ ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT NOTE: V (Pin 42) and GND (Pin 15) are not internally connected. For future device revisions recommended that these pins be CC connected to their respected power supplies (i.e., ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT enables successful block erasure, PENH PEN programming, and lock-bit configuration. functions associated with altering contents—block erase, program, configuration—are accessed via the CUI and verified through the status register. Commands ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 2. Chip Enable Truth Table DEVICE Enabled Disabled Disabled ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 3.5 Read Query The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system interface information, geometry information, and Intel-specific extended query information. 3.6 Read Identifier Codes The ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 3. Bus Operations Mode Notes RP# CE 0,1,2 (10) Read Array 1,2 Enabled Output V or Enabled IH Disable V HH Standby V or Disabled ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 4. Intel StrataFlash™ Memory Command Set Definitions Command Scaleable Bus or Basic Cycles Command Req'd. Set (15) Read Array SCS/BCS 1 Read Identifier SCS/BCS 2 Codes Read Query SCS 2 Read ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT NOTES: 1. Bus operations are defined in Table Any valid address within the device Address within the block Identifier Code Address: see Figure ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.1 Read Array Command Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 5. Summary of Query Structure Output as a Function of Device and Mode Device Query start Query data with type/ location maximum device mode in maximum bus width addressing device ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.2 QUERY STRUCTURE OVERVIEW The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized below. See ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.3 BLOCK STATUS REGISTER The Block Status Register indicates whether a given block is locked and can be accessed for program/erase operations. On SCS devices that do not implement block locking, ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.4 CFI QUERY IDENTIFICATION STRING The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which vendor-specified command set(s) ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.5 SYSTEM INTERFACE INFORMATION The following device information can optimize system interface software. Table 10. System Interface Information Offset Length (bytes) 1Bh 01h V Logic Supply Minimum CC Program/Erase voltage bits ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.6 DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table 11. Device Geometry Definition Offset Length (bytes) 27h 01h Device Size = 2 28h 02h Flash Device ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.7 PRIMARY-VENDOR SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information. Table 12. Primary Vendor-Specific Extended Query ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 12. Primary Vendor-Specific Extended Query (Continued) Offset (1) Length (bytes) (P +C)h 01h V Optimum Program/Erase voltage (highest CC performance) bits 7–4 bits 3–0 (P +D)h 01h V [Programming] Optimum Program/Erase ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.4 Read Status Register Command The status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT V . Specification t defines the block erase OH WHRH suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the automatically outputs status register data when read (see Figure 8). The CPU can ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT A successful set block lock-bit operation requires that the master lock-bit be zero or, if the master lock-bit is set, that RP attempted with HH the ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 15. Configuration Coding Definitions Reserved bits 7– – Reserved DQ 1 – STS Pin Configuration Codes 00 = default, level mode RY/BY# (device ready) ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 16. Status Register Definitions WSMS ESS ECLBS bit 7 bit 6 bit 5 High Z When Status Register Bits Busy? No SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 17. eXtended Status Register Definitions WBS bit 7 High Z Status Register Bits When Busy? No XSR.7 = WRITE BUFFER STATUS 1 = Write buffer available 0 = Write buffer ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Set Time-Out Issue Write Command No E8H, Block Address Read Extended Status Register 0 Write XSR.7 = Buffer Time-Out? 1 Write Word or Byte Count, Block Address Write Buffer Data, Start ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write 40H, Address Write Data and Address Read Status Register 0 SR Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Device Supports Queuing Yes Set Time-Out Issue Block Queue Erase Command 28H, Block Address No Read Extended Status Register Is Queue Erase Block 0=No Available? Time-Out? XSR.7= 1=Yes Another Block Erase? ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Program Read or Program? Read Array Program No Data Loop Done? Yes Write ...

Page 38

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data ...

Page 39

E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) ...

Page 40

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 5.0 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. Intel provides five control inputs ( OE#, and RP#) to accommodate multiple 2 ...

Page 41

E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT The CUI latches commands issued by system software and is not altered PEN CE transitions, or WSM actions. Its state is read 2 array mode upon power-up, ...

Page 42

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.0 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Commercial Operating Temperature During Read, Block Erase, Program, and Lock-Bit Configuration ..... 0 °C to +70 °C Temperature under Bias ........ –10 °C to +80 ...

Page 43

E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.4 DC Characteristics Sym Parameter Notes I Input and V Load 1 LI PEN Current I Output Leakage 1 LO Current I V Standby Current 1,3,5 CCS Power-Down ...

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.4 DC Characteristics (Continued) Sym Parameter Notes Min V Input Low Voltage 7 –0 Input High Voltage 7 2 Output Low Voltage 3,7 OL 3,7 2.4 V Output ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 2.4 2.0 Input 0.8 0.45 AC test inputs are driven for a Logic "1" and V OH TTL (2 and V (0 ...

Page 46

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.5 AC Characteristics— Read-Only Operations Versions (All units in ns unless otherwise noted) # Sym Parameter R1 t Read/Write Cycle Time AVAV R2 t Address to Output Delay AVQV ...

Page 47

E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT NOTES: CE low is defined as the first edge that disables the device (see Table 2, Chip ...

Page 48

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.6 AC Characteristics— Write Operations Versions # Sym RP# High Recovery to WE# (CE ) PHWL PHEL Low (WE#) Low to WE# (CE ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT NOTES: CE low is defined as the first edge that disables the device (see Table 2, Chip ...

Page 50

INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT V IH STS ( RP# ( NOTES: STS is shown in its default mode (RY/BY#). Figure 18. AC Waveform for Reset Operation # Sym. Parameter ...

Page 51

E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.7 Block Erase, Program, and Lock-Bit Configuration Performance # Sym Parameter W16 t Write Buffer Byte Program Time WHQV1 t EHQV1 W16 t Write Buffer Word Program Time WHQV2 t EHQV2 ...

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... E = 56-Lead TSOP DA = 56-Lead SSOP Product line designator for all Intel Flash products Device Density 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Order Code by Density 32 Mbit DA28F320J5-120 G28F320J5-120 E28F320J5-120 52 0 Voltage ( 5V/5V Product Family J = Intel StrataFlash 2 bits-per-cell Valid Operational 64 Mbit 2.7 V – 3.6 ...

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E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 8.0 ADDITIONAL INFORMATION Order Number 210830 1997 Flash Memory Databook AP-374 Flash Memory Write Protection Techniques 292123 292203 AP-644 Intel StrataFlash™ Memory Migration Guide AP-646 Common Flash Interface (CFI) and Command ...

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