28F640J3A120 Intel Corporation, 28F640J3A120 Datasheet

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28F640J3A120

Manufacturer Part Number
28F640J3A120
Description
Intel Strataflash Memory28F128J3 28F640J3 28F320J3
Manufacturer
Intel Corporation
Datasheet
3 Volt Intel StrataFlash
28F128J3, 28F640J3, 28F320J3 (x8/x16)
Product Features
Performance
— 110/115/120/150 ns Initial Access Speed
— 25 ns Asynchronous Page-Mode Reads
— 32-Byte Write Buffer
—6.8 µs per Byte Effective
Programming Time
Software
— Program and Erase suspend support
— Flash Data Integrator (FDI), Common
Flash Interface (CFI) Compatible
Security
— 128-bit Protection Register
—64-bit Unique Device Identifier
—64-bit User Programmable OTP Cells
— Absolute Protection with V
PEN
— Individual Block Locking
— Block Erase/Program Lockout during
Power Transitions
Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the 3 Volt Intel StrataFlash
(J3) device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in
128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-per-cell storage
technology to the flash market segment. Benefits include: more density in less space, high-speed interface,
lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes
advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components
are ideal for code and data applications where high density and low cost are required. Examples include
networking, telecommunications, digital set top boxes, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from
existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash
memory (28F640J5 and 28F320J5) devices.
J3 memory components deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density
upgrades and optimized write capabilities of future Intel StrataFlash
0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device
provides the highest levels of quality and reliability.
Notice: This document contains information on new products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
®
Memory
Architecture
— Multi-Level Cell Technology: High
Density at Low Cost
— High-Density Symmetrical 128-Kbyte
Blocks
—128 Mbit (128 Blocks)
— 4 Mbit (64 Blocks)
—32 Mbit (32 Blocks)
Quality and Reliability
— Operating Temperature:
-40 °C to +85 °C
— 100K Minimum Erase Cycles per Block
— 0.18 µm ETOX™ VII Process (J3C)
— 0.25 µm ETOX™ VI Process (J3A)
Packaging and Voltage
= GND
— 56-Lead TSOP Package
— 64-Ball Intel
®
Easy BGA Package
— 48-Ball Intel
VF BGA Package (32 and
®
64 Mbit) (x16 only)
— V
= 2.7 V – 3.6 V
CC
— V
= 2.7 V – 3.6 V
CCQ
®
memory devices. Manufactured on Intel
Order Number: 290667-013
Datasheet
®
Memory
®
®
February 2003

Related parts for 28F640J3A120

28F640J3A120 Summary of contents

Page 1

Volt Intel StrataFlash 28F128J3, 28F640J3, 28F320J3 (x8/x16) Product Features Performance — 110/115/120/150 ns Initial Access Speed — Asynchronous Page-Mode Reads — 32-Byte Write Buffer —6.8 µs per Byte Effective Programming Time Software — Program and Erase suspend ...

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... Intel's website at http://www.intel.com. Copyright © 2003, Intel Corporation. All rights reserved. Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...

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Contents 1.0 Introduction....................................................................................................................................7 1.1 Document Purpose ...............................................................................................................7 1.2 Nomenclature .......................................................................................................................7 1.3 Conventions..........................................................................................................................7 2.0 Device Description ........................................................................................................................8 2.1 Product Overview .................................................................................................................8 2.2 Ballout Diagrams ..................................................................................................................9 2.3 Signal Descriptions .............................................................................................................12 2.4 Block Diagram ....................................................................................................................13 2.5 Memory Map .......................................................................................................................14 3.0 Device Operations .......................................................................................................................15 ...

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Contents 8.0 Special Modes.............................................................................................................................. 30 8.1 Set Read Configuration ...................................................................................................... 30 8.1.1 Read Configuration................................................................................................ 30 8.2 STS..................................................................................................................................... 30 9.0 Power and Reset.......................................................................................................................... 32 9.1 Power-Up/Down Characteristics......................................................................................... 32 9.2 Power Supply Decoupling................................................................................................... 32 9.3 Reset Characteristics.......................................................................................................... 32 10.0 Electrical Specifications ............................................................................................................. ...

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Revision History Date of Version Revision 07/07/99 -001 08/03/99 -002 09/07/99 -003 12/16/99 -004 03/16/00 -005 06/26/00 -006 2/15/01 -007 04/13/01 -008 Datasheet Description Original Version A –A indicated on block diagram 0 2 Changed Minimum Block Erase time,I OL ...

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Contents Date of Version Revision 07/27/01 -009 10/31/01 -010 03/21/02 -011 12/12/02 -012 01/24/03 -013 6 Description ® Added Figure 4, 3 Volt Intel StrataFlash ® Added Figure 5, 3 Volt Intel StrataFlash Specifications Updated Operating Temperature Range to Extended ...

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Introduction 1.1 Document Purpose This document contains information pertaining to the 3 Volt Intel StrataFlash The purpose of this document is to facilitate the use of this product and describe the features, operations, and specifications of this device. 1.2 ...

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Device Description 2.1 Product Overview The 3 Volt Intel StrataFlash Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed ...

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BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lock- bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is suspended (and programming is inactive), program is ...

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Figure 1. 3 Volt Intel StrataFlash VSS A10 A11 BYTE# D0 D10 G A23 A0 D2 128M ...

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Figure 3. 3 Volt Intel StrataFlash A14 A12 A9 VPEN VCC B A19 A15 A11 WE# RP# C A13 A16 A10 A22 A21 D A17 D2 D14 D5 D11 E VCCQ D12 D15 D6 ...

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Signal Descriptions Table 1 lists the active signals used and provides a description of each. Table 1. Signal Descriptions (Sheet Symbol Type A0 INPUT A[23:1] INPUT INPUT/ D[7:0] OUTPUT INPUT/ D[15:8] OUTPUT CE0, ...

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Table 1. Signal Descriptions (Sheet Symbol Type VCCQ POWER GND SUPPLY NC RFU 2.4 Block Diagram Figure 4. 3 Volt Intel StrataFlash VCCQ A[2:0] Y-Decoder A[MAX:MIN] Input Buffer Address Latch X-Decoder Address Counter Datasheet Name and Function ...

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Memory Map Figure 5. 3 Volt StrataFlash A [MAX : MIN] FFFFFF FE0000 7FFFFF 7E0000 3FFFFF 3E0000 03FFFF 020000 01FFFF 000000 Byte-Wide (x8) Mode 14 ® Memory Map A [MAX : MIN] 7FFFFF 128-Kbyte Block 127 ...

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Device Operations This section provides an overview of device operations. The on-chip Write State Machine (WSM) manages all block-erase and word-program algorithms. The system CPU provides control of all in- system read, write, and erase operations of the device ...

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Table 3. Chip Enable Truth Table CE2 NOTE: For single-chip applications, CE2 and CE1 can be strapped to GND. 3.1.1 Read ...

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Standby CE0, CE1, and CE2 can disable the device (see which substantially reduces device power consumption. D[15:0] outputs are placed in a high- impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM ...

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Table 4. Intel StrataFlash Scalable or Basic Command Command (2) Set Read Status Register SCS/BCS Clear Status Register SCS/BCS Write to Buffer SCS/BCS Word/Byte Program SCS/BCS Block Erase SCS/BCS Block Erase, Program SCS/BCS Suspend Block Erase, Program ...

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Read Operations The device supports four types of read modes: read array, read identifier, read status or read query. Upon power-up or return from reset, the device defaults to read array mode. To change the device’s read mode, the ...

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Codes command functions independently of the V the WSM is off or the device is suspended. Following the Read Identifier Codes command, the following information can be read Table 5. Identifier Codes Code Manufacture Code Device Code ...

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Table 6. Status Register Definitions WSMS ESS ECLBS bit 7 bit 6 bit 5 High Z When Status Register Bits Busy? SR7 = WRITE STATE MACHINE STATUS Ready 0 = Busy Yes SR6 = ERASE SUSPEND STATUS ...

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Read Query/CFI The query register contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications and other product information. The data contained in this register conforms to the Common ...

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Next, a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the ...

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Program Resume To resume (i.e., continue) a program suspend operation, execute the Program Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation ...

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At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a ...

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Security Modes This device offers both hardware and software security features. Block lock operations, PRs, and VPEN allow the user to implement various levels of data protection. The following section describes security features in detail. 7.1 ...

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If a clear block lock-bits operation is aborted due to V block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. 7.3 Protection Register Program ...

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Figure 6. Protection Register Memory Map NOTE not used in x16 mode when accessing the protection register map (See addressing). For x8 mode A0 is used (See 28 A[23:1]: 128 Mbit Word A[22:1]: 64 Mbit ...

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Table 8. Word-Wide Protection Register Addressing Word Use LOCK Both 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User NOTE: All address lines not specified in the above table must be 0 when ...

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Array Protection The V signal is a hardware mechanism to prohibit array alteration. When the V PEN below the V PENLK operation, V must be set to a valid voltage level. To determine the status of ...

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To reconfigure the Status (STS) signal to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, ...

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Power and Reset This section provides an overview of some system level considerations in regards to the flash device. This section provides a brief description of power-up, power-down, decoupling and reset design considerations. 9.1 Power-Up/Down Characteristics ...

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Electrical Specifications 10.1 Absolute Maximum Ratings This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a ...

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Operating Conditions Table 13. Temperature and V Symbol Parameter T Operating Temperature Supply Voltage (2 CC1 V V Supply Voltage (2.7 V 3.6 V) CCQ CCQ 34 Operating Conditions ...

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DC Current Characteristics Table 14. DC Current Characteristics Symb Parameter ol I Input and V Load Current LI PEN I Output Leakage Current Standby Current CCS Power-Down Current CCD Page ...

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DC Voltage Characteristics Table 15. DC Voltage Characteristics Symbol V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Lockout during Program, PEN V PENLK ...

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AC Characteristics 11.1 Read Operations Table 16. Read Operations (Sheet (All units in ns unless otherwise noted) # Sym R1 t AVAV R2 t AVQV R3 t ELQV R4 t GLQV R5 t PHQV R6 t ...

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Table 16. Read Operations (Sheet (All units in ns unless otherwise noted) # Sym R15 t APA R16 t GLQV NOTES: CE low is defined as the first edge of CE0, CE1, or CE2 ...

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Write Operations Table 17. Write Operations Versions # Symbol RP# High Recovery to WE# (CE PHWL PHEL (WE#) Low to WE# (CE ELWL WLEL Write Pulse Width ...

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Block Erase, Program, and Lock-Bit Configuration Performance Table 18. Configuration Performance # Sym Write Buffer Byte Program Time W16 (Time to Program 32 bytes/16 words) t WHQV3 W16 Byte Program Time (Using Word/Byte Program Command) t ...

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Figure 8. AC Waveform for Write Operations ADDRESSES [A] Disabled ( (WE#) [E(W)] X Enabled (V OE# [G] Disabled (V WE#, (CE ) [W(E)] X Enabled (V DATA [D/Q] STS [R] RP# [ PENLK V [V] ...

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Reset Operation Figure 9. AC Waveform for Reset Operation V STS ( RP# (P) V NOTE: STS is shown in its default mode (RY/BY#). Table 19. Reset Specifications # Sym RP# Pulse Low Time ...

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Figure 11. Transient Equivalent Testing Load Circuit NOTE: C Includes Jig Capacitance L Test Configuration 2.7 V 3.6 V CCQ CC 11.6 Capacitance T = +25 ° MHz A Symbol C Input Capacitance ...

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Appendix A Write State Machine (WSM) A.1 TBD 44 Datasheet ...

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Appendix B Common Flash Interface The Common Flash Interface(CFI) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device independent, JEDEC ID-independent, and forward- ...

Page 46

Table 20. Summary of Query Structure Output as a Function of Device and Mode Device Query start location in Type/ maximum device bus Mode width addresses x16 device x16 mode x16 device x8 mode NOTE: 1. The ...

Page 47

Table 22. Query Structure Offset 00h 01h (2) (BA+2)h Block Status Register 04-0Fh Reserved 10h CFI Query Identification String 1Bh System Interface Information 27h Device Geometry Definition Primary Intel-Specific Extended (3) P Query Table NOTES: 1. Refer to the Query ...

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Table 24. CFI Identification (Sheet Offset Length 0000h means no second vendor-specified algorithm exists 19h 2 Secondary algorithm Extended Query Table address. 0000h means none exists B.5 System Interface Information The following device information ...

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Table 26. Device Geometry Definition (Sheet Offset Length Number of erase block regions within device means no erase blocking; the device erases in “bulk” specifies the number of device or partition ...

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Table 27. Primary Vendor-Specific Extended Query (Sheet (1) Offset Length P = 31h (P+5)h (P+6)h 4 (P+7)h (P+8)h (P+9)h 1 (P+A)h 2 (P+B)h (P+C)h 1 (P+D)h 1 NOTE: 1. Future devices may not support ...

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Table 28. Protection Register Information (1) Offset Length P = 31h (P+E)h 1 (P+F)h (P+10)h 4 (P+11)h (P+12)h NOTE: 1. The variable pointer which is defined at CFI offset 15h. Table 29. Burst Read Information (1) Offset ...

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Appendix C Flow Charts Figure 12. Write to Buffer Flowchart - Read Status Register Command not required - Perf orm read operation - Read Ready Status on signal D7 - Fill write buf ...

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Figure 13. Status Register Flowchart Start Command Cycle - Issue Status Register Command - Address = any dev ice address - Data = 0x70 Data Cycle - Read Status Register SR[7:0] SR7 = ' Set/Reset SR6 = ...

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Figure 14. Byte/Word Program Flowchart Start Write 40H, Address Write Data and Address Read Status Register SR Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) ...

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Figure 15. Program Suspend/Resume Flowchart Start Write B0H Read Status Register SR SR Write FFH Read Data Array Done Reading Yes Write D0H Programming Resumed Datasheet Bus Operation Write Read Standby Standby 0 Write Read 0 ...

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Figure 16. Block Erase Flowchart Start Issue Single Block Erase Command 20H, Block Address Write Confirm D0H Block Address Read Status Register SR Full Status Check if Desired Erase Flash Block(s) Complete 56 Bus Operation ...

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Figure 17. Block Erase Suspend/Resume Flowchart Start Write B0H Read Status Register SR.7 = SR.6 = Read Read or Program? Read Array Data Done? Write D0H Block Erase Resumed Datasheet Bus Operation Write Read Standby Standby 0 Write 1 0 ...

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Figure 18. Set Block Lock-Bit Flowchart Start Write 60H, Block Address Write 01H, Block Address Read Status Register SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data ...

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Figure 19. Clear Lock-Bit Flowchart Start Write 60H Write D0H Read Status Register SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR SR.4,5 = ...

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Figure 20. Protection Register Programming Flowchart Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status ...

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Appendix D Mechanical Information Figure 21. 56-Lead TSOP Package Drawing and Specifications Z Pin 1 See Detail A Detail A Table 30. 56-Lead TSOP Dimension Table Sym Package Height A Standoff A 1 Package Body Thickness A 2 Lead Width ...

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Figure 22. 3 Volt Intel StrataFlash Ball A1 Corner Top View - Ball side down A1 A2 Side View Dimensions Table Package Height ...

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Figure 23. 3 Volt Intel StrataFlash Ball A1 Corner Top View - Bump S ide Down A1 A2 Side View Dimensions Table Package Height Ball Height ...

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Appendix E Design Considerations E.1 Three-Line Output Control The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides ...

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E RP# Transitions CC PEN Block erase, program, and lock-bit configuration are not guaranteed if V the specified operating ranges, or RP# program, or lock-bit configuration, STS (in default mode) will remain low for a maximum ...

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Appendix F Additional Information Order Number 298130 298136 297833 290737 292280 292237 290606 297859 292222 292221 292218 292204 298161 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact ...

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Appendix G Ordering Information Package E = 56-Lead TSOP TE = 56-Lead TSOP RC = 64-Ball Easy BGA GE = 48-Ball VF BGA Product line designator ® for all Intel Flash products Device Density 128 = x8/x16 (128 Mbit) 640 ...

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Datasheet ...

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