NPIXP2400BB Intel Corporation, NPIXP2400BB Datasheet

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NPIXP2400BB

Manufacturer Part Number
NPIXP2400BB
Description
Intel IXP2400 Network Processor
Manufacturer
Intel Corporation
Datasheet
Intel
Product Features
Notice: Please verify with your local Intel sales office that you have the latest datasheet before
finalizing a design.
Eight integrated Microengine Version 2
Processors
Integrated Intel XScale core
Two uni-directional 32-bit low-voltage
transistor-transistor logic (LVTTL) data
interfaces
— Operating frequencies of 400 and 600 MHz
— Configurable to four or eight threads per
— 640 x 32-bit local memory per Microengine
— Sixteen-entry CAM per Microengine with
— Next Neighbor bus: A dedicated datapath
— CRC unit per Microengine supporting
— 4K-instruction control store per Microengine
— Support for Generalized Thread Signaling
— Reflector access to read or write data between
— Operating frequencies of 400 and 600 MHz
— High-performance, low-power, 32-bit
— 32-Kbyte instruction cache
— 32-Kbyte data cache
— 2-Kbyte mini data cache
— Speeds from 25 to 133 MHz supported
— Separately configurable for POS-PHY,
— Interprocessor “Cbus” communication
Microengine
single cycle lookup
between adjacent Microengines
CRC-16 (CCITT) and CRC-32
any Microengines
embedded RISC processor
UTOPIA 1/2/3, or CSIX-L1-B Protocol
support
®
IXP2400 Network Processor
The Intel
network services by providing high programming flexibility, code re-use, and
high-performance processing. IXP2400 Network Processor supports a wide
variety of WAN and LAN applications requiring support for a broad range of
speeds, currently ranging from OC-3 to OC-48. High performance and
scalability is achieved through an innovative Microengine architecture that
includes a multi-threaded distribution cache architecture that enables pipeline
features in software. The Microengines feature innovative inter-thread
communication capabilities for efficient processing at high line rates, and
general-purpose hardware elements that support advanced networking
algorithms. The Microengines play a key role in the Intel
Architecture (IXA) store and forward architecture, providing flexible, rich
network processing in converged communications environments.
®
IXP2400 Network Processor enables faster deployment of intelligent
Industry-standard PCI Bus Version 2.2
interface for 64-bit, 66-MHz I/O
Industry-standard double-data-rate (DDR)
SDRAM memory interface
Two industry-standard 32-bit quad-data-rate
(QDR) SRAM interfaces
Additional integrated features
1356-Ball FCBGA2 package
— Peak bandwidth of 2.4 GB/s
— Clock speeds of 100, 150 MHz supported
— Error correction code (ECC)
— Addressable from the Intel XScale core, MEs,
— Peak bandwidth of 1.6 GB/s per channel
— 100- or 133-MHz SRAM when IXP2400 is
— Hardware support for Linked List and Ring
— Atomic bit operations
— Atomic arithmetic support
— Addressable from the Intel XScale core, MEs,
— Hardware hash unit (48, 64 and 128 bit)
— 16-Kbyte scratchpad memory
— Serial port for debug
— Eight general-purpose I/O pins
— Four 32-bit timers
— Dimensions of 37.5 mm x 37.5 mm
— 1 mm solder ball pitch
when IXP2400 is running at 600 MHz; 100
MHz when IXP2400 is running at 400 MHz
and PCI
running at 400 MHz; 100-, 150- or 200-MHz
SRAM when IXP2400 is running at 600 MHz
operations
and PCI
Document Number: 301164-011
®
Exchange
Datasheet
February 2004

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NPIXP2400BB Summary of contents

Page 1

Intel IXP2400 Network Processor Product Features ® The Intel IXP2400 Network Processor enables faster deployment of intelligent network services by providing high programming flexibility, code re-use, and high-performance processing. IXP2400 Network Processor supports a wide variety of WAN and ...

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... Paragon, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, Sound Mark, The Computer Inside., The Journey Inside, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...

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Contents 1.0 Product Description ...........................................................................................................7 2.0 Functional Units...............................................................................................................10 2.1 Functional Overview........................................................................................... 10 2.2 Intel XScale 2.2.1 Instruction Cache .................................................................................. 12 2.2.2 Data Cache ........................................................................................... 12 2.2.3 Debug.................................................................................................... 12 2.2.4 Memory Management ........................................................................... 13 2.2.5 Branch Target Buffer ............................................................................. 13 2.3 ...

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Intel IXP2400 Network Processor 3.3.3 SlowPort Clock Behavior During Reset................................................. 69 3.3.4 Pullup/Pulldown and Unused Pin Guidelines ........................................ 69 3.4 Ball Information .................................................................................................. 70 3.5 Ball List Tables................................................................................................... 72 3.5.1 Balls Listed in Alphanumeric Order by Signal Name............................. 72 ...

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Chip Select Valid Before and After Clock Rising Edge ...................................111 25 Clock Cycle Time ............................................................................................111 26 Skew Between Any System Memory Differential Clock Pair...........................111 27 Clock High Time ..............................................................................................112 28 Clock Low Time...............................................................................................112 29 Data Strobe Falling Edge Output ...

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Intel IXP2400 Network Processor 18 1x32 SPHY Slave Mode..................................................................................... 54 19 2x16 SPHY Slave Mode..................................................................................... 56 20 4x8 SPHY Slave Mode....................................................................................... 58 21 1x16+2x8 SPHY Slave Mode............................................................................. 60 22 CBus Pinout ....................................................................................................... 62 23 PCI Signals ........................................................................................................ 63 24 ...

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Product Description ® The Intel IXP2400 Network Processor is a second-generation high-performance device. The IXP2400 is a highly integrated, programmable data processor that provides high-performance parallel processing power and flexibility to a wide variety of OC-48 (2.5 Gb/s) networking, ...

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Intel IXP2400 Network Processor Figure 2. IXP2400 Network Processor Functional Signal Groups Diagram 1 Power Supplies Media Switch Fabric Interface Flow- Control DDRAM Interface QDRAM Interface Two of these. "n" VCCA VCC3.3 VCC2.5 VCC1.5 ...

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Figure 3. IXP2400 Network Processor Functional Signal Groups Diagram 2 SYS_RESET_OUT_L Clock Signals TDI_T_SCAN_EN IEEE 1149.1 and Test Signals PLL_DIV_BYPASS Datasheet SYS_RESET_L SYS_CLK ® Intel IXP2400 TCK Network TMS_T_CLK Processor TRST_L T_SYS_REFCLK T_LOAD T_DIAG_CLK THERMDA THERMDC PLL_BYPASS ® Intel IXP2400 ...

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Intel IXP2400 Network Processor 2.0 Functional Units 2.1 Functional Overview This section provides a brief overview of the IXP2400 Network Processor internal hardware. Figure simple block diagram that shows the device’s major internal blocks. Figure 4. ...

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CAP — Chip-wide Control and status registers. These provide special inter-processor communication features to allow flexible and efficient inter-Microengine and Microengine-to-Intel-XScale-core communication. ® • Intel XScale Core Peripherals (XPI) — Interrupt Controller, Timers, UART, General-Purpose IO (GPIO) and interface ...

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Intel IXP2400 Network Processor ® Figure 5. Intel XScale Core Internal Block Diagram Instruction Cache 32 Kbytes 32 ways Lockable by line Power Management Idle / Drowsy / Sleep JTAG Performance Monitoring Debug Hardware Breakpoints Branch History Table * ...

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Memory Management The Intel XScale core implements the Memory Management Unit (MMU) Architecture specified in the ARM Architecture Reference Manual. The MMU provides access protection and virtual to physical address translation. The MMU Architecture also specifies the caching policies ...

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Intel IXP2400 Network Processor Figure 6. Microengine Block Diagram NN_Data_In 640 Local Mem d 128 e GPRs c (A Bank Lm_addr_1 Lm_addr_0 CRC_Remainder CRC Unit (Shift, Add, Subtract, Multiply Logicals, S_Push Local CSRs 2.3.1 Control Store ...

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Microengine Contexts There are eight hardware Contexts available in the ME. To allow for efficient context swapping, each Context has its own register set, Program Counter, and context-specific local registers. Having a copy per Context eliminates the need to ...

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Intel IXP2400 Network Processor Context and a working copy of each. When a Context goes to Sleep state, the value of the working copies is put into the Context’s copy of LM_Addr. When the Context returns to the Executing ...

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Read and writes to DRAM generated by the MEs, the Intel XScale core, and PCI units, are presented as requests to the DDR controller, which ...

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Intel IXP2400 Network Processor • Samsung* 36-Mb QDRII x9 K7R320982M-FC20 or 36-Mb QDRII x18 K7R321882M-FC20 SRAM • IDT* IDT71T6280H 9-Mb pipelined QDR SRAM burst of 2 (512K x 18) • Cypress* CY7C1302V25 9-Mb pipelined SRAM with QDR architecture (512K ...

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RAMs, so some address pins (23:20) are configurable as either address- or port-enable based on CSR setting as shown in that all of the SRAMs on a given channel must be ...

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Intel IXP2400 Network Processor • A Flow Control Interface, which provides a point-to-point connection used to pass CSIX-L1-B flow control C-Frames either between two IXP2400 network processors or between a IXP2400 and a CSIX-L1-B switch fabric. • Each 32-bit ...

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XPI Unit 2.8.1 GPIO The IXP2400 contains eight General-Purpose IO (GPIO) pins. These can be programmed as either input or output, and can be used for slow-speed IO, such as LEDs or input switches. They can also be used ...

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Intel IXP2400 Network Processor Figure 8. Example SlowPort Connection SP_RD_L SP_WR_L SP_CS_L[0] SP_CS_L[1] SP_A[1:0] SP_AD[7:0] SP_ALE_L SP_CLK ® Intel IXP2400 and ® Intel IXP2800 Network Processors SP_ACK_L 22 CE# D[7:0] 74f377 CP Q[7:0] A[24:18] CE# D[7:0] 74f377 CP Q[7:0] ...

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Signal Description 3.1 Ballout Functional Groupings Diagram Figure 9 provides a high-level overview of the general groupings of the balls by function. Note that the following ball locations are unpopulated: A1, Y1, W1, V1, Y37, W37, V37, AU[18:20], and ...

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Intel IXP2400 Network Processor IXP2400 signals are categorized into one of several groups: DRAM, SRAM, Media and Switch Fabric Interface, PCI, GPIO, SlowPort (Serial ROM), Serial Port, Clocks, and JTAG and Test. 3.2.1 DDR SDRAM There is one double-data-rate ...

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Table 5. SRAM Signals Signal Name Sn_K[1:0] Sn_K_L[1:0] Sn_C[1:0] Sn_C_L[1:0] Sn_CIN[1:0] Sn_CIN_L[1:0] Sn_DI[15:0] Sn_PI[1:0] Sn_DO[15:0] Sn_PO[1:0] Sn_BWE_L[1:0] Sn_RPE_L[1:0] Sn_WPE_L[1:0] Sn_A[23:0] Sn_Vref Sn_ZQ[1:0] Total (per channel) 1. QDR uses a similar compensation scheme as DDR. However, the voltage references are different. ...

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Intel IXP2400 Network Processor Table 6. MSF Data Signals Pin Name I/O RXCLK23 I RXCLK01 I RXENB[3:0] O RXSOF[3:0] I RXEOF[3:0] I RXVAL[3:0] I RXERR[3:0] I RXPRTY[3:0] I RXFA[3:0] I RXADDR[3:0] O RXPFA I RXPADL[1:0] I RXDATA[31:0] I TXCLK23 ...

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Table 6. MSF Data Signals (Continued) Pin Name I/O 1 RXRCOMP I MSF_CLK_B I 2 YPASS RSVD[3:0] Total (per channel) NOTES: 1. The MSF TXRCOMP and RXRCOMP pins should be separately connected to ground through external 45Ω±1% resistor and one ...

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Intel IXP2400 Network Processor Table 7. 1x32 SPHY UTOPIA/POS-PHY Master Mode Port Port 3 (unused) Port 2 (unused) Port 1 (unused) Port 0 RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] MPHY (unused) 28 Master Pin Direction Name RXCLK23 Input unused; tie to ground ...

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Table 7. 1x32 SPHY UTOPIA/POS-PHY Master Mode (Continued) Master Pin Port Port 3 (unused) TXPRTY[3] Port 2 (unused) TXPRTY[2] Port 1 (unused) TXPRTY[1] Port 0 TXPRTY[0] TXPADL[1:0] TXDATA[31:0] MPHY (unused) TXADDR[3:0] Datasheet Direction Name TXCLK23 Input unused; tie to ground ...

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Intel IXP2400 Network Processor 2x16 SPHY UTOPIA/POS Master Mode Table 8. Port Port 3 (unused) Port 2 RXDATA[31:16] Port 1 Port 0 RXDATA[15:0] 30 Master Pin Direction Name RXCLK23 Input RXENB[3] Output unused; no connect RXSOF[3] Input unused; tie ...

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SPHY UTOPIA/POS Master Mode (Continued) Table 8. Master Pin Port RXADDR[3:0] MPHY (unused) Port 3 (unused) TXPRTY[3] Port 2 TXPRTY[2] TXPADL[1] TXDATA[31:16] Port 1 (unused) TXPRTY[1] Port 0 TXPRTY[0] TXPADL[0] TXDATA[15:0] MPHY (unused) TXADDR[3:0] Datasheet Direction Name Output unused; ...

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Intel IXP2400 Network Processor 4x8 SPHY UTOPIA/POS-PHY Master Mode Table 9. Port Port 3 RXDATA[31:24] Port 2 RXDATA[23:16] Port 1 RXDATA[15:8] 32 Master Pin Direction Slave Mode Function and Description Name RXCLK23 Input RXENB[3] Output RXSOF[3] Input RXEOF[3] Input ...

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SPHY UTOPIA/POS-PHY Master Mode (Continued) Table 9. Master Pin Port Port 0 RXPRTY[0] RXPADL[0] RXDATA[7:0] RXADDR[3:0] MPHY (unused) Port 3 TXPRTY[3] TXDATA[31:24] Port 2 TXPRTY[2] TXPADL[0] TXDATA[23:16] Datasheet Direction Slave Mode Function and Description Name RXCLK01 Input RXENB[0] Output ...

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Intel IXP2400 Network Processor 4x8 SPHY UTOPIA/POS-PHY Master Mode (Continued) Table 9. Port Port 1 TXDATA[15:8] Port 0 TXDATA[7:0] MPHY (unused) TXADDR[3:0] Table 10. 1x16+2x8 SPHY UTOPIA/POS Master Mode Port Port 3 RXDATA[31:24] 34 Master Pin Direction Slave Mode ...

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Table 10. 1x16+2x8 SPHY UTOPIA/POS Master Mode (Continued) Master Pin Port Port 2 RXPRTY[2] RXPADL[1] RXDATA[23:16] Port 1 (unused) RXPRTY[1] Port 0 RXPRTY[0] RXPADL[0] RXDATA[15:0] RXADDR[3:0] MPHY (unused) Datasheet Direction Slave Mode Function and Description Name RXCLK23 Input RXENB[2] Output ...

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Intel IXP2400 Network Processor Table 10. 1x16+2x8 SPHY UTOPIA/POS Master Mode (Continued) Port Port 3 TXDATA[31:24] Port 2 TXDATA[23:16] Port 1 (unused) Port 0 TXDATA[15:0] MPHY (unused) TXADDR[3:0] 36 Master Pin Direction Slave Mode Function and Description Name TXCLK23 ...

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Table 11. x32 UTOPIA Level 3 MPHY Mode Master Pin Port Port 3 (unused) RXPRTY[3] Port 2 (unused) RXPRTY[2] Port 1 (unused) RXPRTY[1] Datasheet Direction Name RXCLK23 Input unused; tie to ground RXENB[3] Output unused; no connect RXSOF[3] Input unused; ...

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Intel IXP2400 Network Processor Table 11. x32 UTOPIA Level 3 MPHY Mode (Continued) Port Port 0 (MPHY) RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] Port 3 (unused) Port 2 (unused) Port 1 (unused) 38 Master Pin Direction Name RXCLK01 Input RXENB[0] Output RXSOF[0] ...

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Table 11. x32 UTOPIA Level 3 MPHY Mode (Continued) Master Pin Port TXPRTY[0] Port 0 (MPHY) TXPADL[1:0] TXDATA[31:0] TXADDR[3:0] Table 12. x32 POS-PHY Level 3 MPHY Mode Master Pin Port Port 3 (unused) RXPRTY[3] Port 2 (unused) RXPRTY[2] Datasheet Direction ...

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Intel IXP2400 Network Processor Table 12. x32 POS-PHY Level 3 MPHY Mode (Continued) Port Port 1 (unused) Port 0 (MPHY) RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] Port 3 (unused) Port 2 (unused) 40 Master Pin Direction Name RXCLK01 Input RXENB[1] Output unused; ...

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Table 12. x32 POS-PHY Level 3 MPHY Mode (Continued) Master Pin Port Port 1 (unused) TXPRTY[1] TXPRTY[0] Port 0 (MPHY) TXPADL[1:0] TXDATA[31:0] TXADDR[3:0] Table 13. 1x32 CSIX Mode Master Pin Port Port 3 (unused) RXPRTY[3] Datasheet Direction Name TXCLK01 Input ...

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Intel IXP2400 Network Processor Table 13. 1x32 CSIX Mode (Continued) Port Port 2 (unused) Port 1 (unused) Port 0 (CSIX Rx) RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] TXCDAT[3:0] CBus Tx 42 Master Pin Direction Name RXCLK23 Input unused; tie to ground RXENB[2] ...

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Table 13. 1x32 CSIX Mode (Continued) Master Pin Port Port 3 (unused) TXPRTY[3] Port 2 (unused) TXPRTY[2] Port 1 (unused) TXPRTY[1] TXPRTY[0] Port 0 (CSix Tx) TXPADL[1:0] TXDATA[31:0] TXADDR[3:0] Datasheet Direction Name TXCLK23 Input unused; tie to ground TXENB[3] Output ...

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Intel IXP2400 Network Processor Table 13. 1x32 CSIX Mode (Continued) Port RXCDAT[3:0] CBus Rx Table 14. x16 UTOPIA Level 2 MPHY-32 + x16 SPHY (UTOPIA or POS-PHY) Mode Port Port 3 (unused) Port 2 (SPHY) RXDATA[31:16] Port 1 (unused) ...

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Table 14. x16 UTOPIA Level 2 MPHY-32 + x16 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 0 (MPHY) RXPRTY[0] RXPADL[0] RXDATA[15:0] RXADDR[3:0] Port 3 (unused) TXPRTY[3] Port 2 (SPHY) TXPRTY[2] TXPADL[1] TXDATA[31:16] Port 1 (unused) TXPRTY[1] Datasheet Master Mode ...

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Intel IXP2400 Network Processor Table 14. x16 UTOPIA Level 2 MPHY-32 + x16 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 0 (MPHY) TXDATA[15:0] TXADDR[3:0] Table 15. x16 UTOPIA Level 2 MPHY-32 + 2x8 SPHY (UTOPIA or POS-PHY) Mode ...

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Table 15. x16 UTOPIA Level 2 MPHY-32 + 2x8 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 2 (SPHY) RXPRTY[2] RXPADL[1] RXDATA[23:16] Port 1 (unused) RXPRTY[1] Port 0 (MPHY) RXPRTY[0] RXPADL[0] RXDATA[15:0] RXADDR[3:0] Datasheet Master Mode Function Pin Name Direction ...

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Intel IXP2400 Network Processor Table 15. x16 UTOPIA Level 2 MPHY-32 + 2x8 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 3 (SPHY) TXDATA[31:24] Port 2 (SPHY) TXDATA[23:16] Port 1 (unused) Port 0 (MPHY) TXDATA[15:0] TXADDR[3:0] 48 Master Mode ...

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Table 16. x16 POS-PHY Level 2 MPHY-32 + x16 SPHY (UTOPIA or POS-PHY) Mode Port Port 3 (unused) RXPRTY[3] Port 2 (SPHY) RXPRTY[2] RXPADL[1] RXDATA[31:16] Port 1 (unused) RXPRTY[1] Datasheet Master Mode Function and Pin Name Direction Description RXCLK23 Input ...

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Intel IXP2400 Network Processor Table 16. x16 POS-PHY Level 2 MPHY-32 + x16 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 0 (MPHY) RXDATA[15:0] RXADDR[3:0] Port 3 (unused) Port 2 (SPHY) TXDATA[31:16] Port 1 (unused) 50 Master Mode Function ...

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Table 16. x16 POS-PHY Level 2 MPHY-32 + x16 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port TXPRTY[0] Port 0 (MPHY) TXPADL[0] TXDATA[15:0] TXADDR[3:0] Table 17. x16 POS-PHY Level 2 MPHY-32 + 2x8 SPHY (UTOPIA or POS-PHY) Mode Port Port 3 ...

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Intel IXP2400 Network Processor Table 17. x16 POS-PHY Level 2 MPHY-32 + 2x8 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 2 (SPHY) RXDATA[23:16] Port 1 (unused) Port 0 (MPHY) RXDATA[15:0] RXADDR[3:0] 52 Master Mode Function Pin Name Direction ...

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Table 17. x16 POS-PHY Level 2 MPHY-32 + 2x8 SPHY (UTOPIA or POS-PHY) Mode (Continued) Port Port 3 (SPHY) TXPRTY[3] TXDATA[31:24] Port 2 (SPHY) TXPRTY[2] TXPADL[1] TXDATA[23:16] Port 1 (unused) TXPRTY[1] TXPRTY[0] Port 0 (MPHY) TXPADL[0] TXDATA[15:0] TXADDR[3:0] Datasheet Master ...

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Intel IXP2400 Network Processor Table 18. 1x32 SPHY Slave Mode Port Port 3 (unused) Port 2 (unused) Port 1 (unused) Port 0 RXDATA[31:0] RXPADL[1:0] RXADDR[3:0] MPHY (unused) 54 Master Pin Direction Slave Mode Function and Description Name RXCLK23 Input ...

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Table 18. 1x32 SPHY Slave Mode (Continued) Master Pin Port Port 3 (unused) TXPRTY[3] Port 2 (unused) TXPRTY[2] Port 1 (unused) TXPRTY[1] Port 0 TXPRTY[0] TXPADL[1:0] TXDATA[31:0] MPHY (unused) TXADDR[3:0] Datasheet Direction Slave Mode Function and Description Name TXCLK23 Input ...

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Intel IXP2400 Network Processor Table 19. 2x16 SPHY Slave Mode Port Port 3 (unused) Port 2 RXDATA[31:16] Port 1 Port 0 RXDATA[15:0] 56 Master Pin Direction Slave Mode Function and Description Name RXCLK23 Input TXCLK23 RXENB[3] Output unused; no ...

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Table 19. 2x16 SPHY Slave Mode (Continued) Master Pin Port RXADDR[3:0] MPHY (unused) Port 3 (unused) TXPRTY[3] Port 2 TXPRTY[2] TXPADL[1] TXDATA[31:16] Port 1 (unused) TXPRTY[1] Port 0 TXPRTY[0] TXPADL[0] TXDATA[15:0] MPHY (unused) TXADDR[3:0] Datasheet Direction Slave Mode Function and ...

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Intel IXP2400 Network Processor Table 20. 4x8 SPHY Slave Mode Port Port 3 RXDATA[31:24] Port 2 RXDATA[23:16] Port 1 RXDATA[15:8] 58 Master Pin Direction Slave Mode Function and Description Name RXCLK23 Input TXCLK23 RXENB[3] Output TXFA[3] RXSOF[3] Input TXSOF[3] ...

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Table 20. 4x8 SPHY Slave Mode (Continued) Master Pin Port Port 0 RXPRTY[0] RXPADL[0] RXDATA[7:0] RXADDR[3:0] MPHY (unused) Port 3 TXPRTY[3] TXDATA[31:24] Port 2 TXPRTY[2] TXPADL[0] TXDATA[23:16] Port 1 TXPRTY[1] TXDATA[15:8] Datasheet Direction Slave Mode Function and Description Name RXCLK01 ...

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Intel IXP2400 Network Processor Table 20. 4x8 SPHY Slave Mode (Continued) Port Port 0 TXDATA[7:0] MPHY (unused) TXADDR[3:0] Table 21. 1x16+2x8 SPHY Slave Mode Port Port 3 RXDATA[31:24] Port 2 RXDATA[23:16] 60 Master Pin Direction Slave Mode Function and ...

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Table 21. 1x16+2x8 SPHY Slave Mode (Continued) Master Pin Port Port 1 (unused) RXPRTY[1] Port 0 RXPRTY[0] RXPADL[0] RXDATA[15:0] RXADDR[3:0] MPHY (unused) Port 3 TXPRTY[3] TXDATA[31:24] Port 2 TXPRTY[2] TXPADL[1] TXDATA[23:16] Datasheet Direction Slave Mode Function and Description Name RXCLK01 ...

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Intel IXP2400 Network Processor Table 21. 1x16+2x8 SPHY Slave Mode (Continued) Port Port 1 (unused) Port 0 TXDATA[15:0] MPHY (unused) TXADDR[3:0] Table 22. CBus Pinout Pin Name TXCDATA[3:0] TXCDATA[7:4] TXCSOF TXCSRB TXCFC TXCPAR RXCDATA[3:0] RXCDATA[7:4] RXCSOF RXCSRB RXCFC RXCPAR ...

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PCI PCI Bus can be used to interface to industry-standard IO devices host processor. See 23 for a list of signals. PCI signaling levels are defined in PCI Rev. 2.2 specification. Table 23. PCI Signals Signal ...

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Intel IXP2400 Network Processor 1. The PCI_RCOMP pin should be connected to ground through external a 24Ω ±1% resistor and one 0603 0.1 µF decoupling capacitor. Place the resistor and capacitor as close to the IXP2400 as possible, within ...

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Table 25. GPIO Signals Signal Name GPIO[7:0] Total (per channel) 3.2.7 Serial Port Signals Serial port is the RS-232–compatible UART used for debug and diagnostics. See Table 26. Serial Port Signals Signal Name SERIAL_RX SERIAL_TX Total (per channel) 3.2.8 Clock ...

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Intel IXP2400 Network Processor Table 28. Test, JTAG, and Miscellaneous Signals Signal Name TCK TMS_T_CLK TDI_T_SCAN_EN TDO TRST_L T_SYS_REFCLK T_LOAD T_DIAG_CLK 1 THERMDA 1 THERMDC PLL_BYPASS PLL_DIV_BYPASS TST_RESET_L VCCA VSSA VCC3_3 66 I/O Description Test interface reference clock. This ...

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Table 28. Test, JTAG, and Miscellaneous Signals (Continued) Signal Name VCC2_5 VCC1_5 Total (per channel) 1. For these signals, the thermal equation used to convert voltage to temperature is -551.225x + 410.694 For example, if the voltage is ...

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Intel IXP2400 Network Processor Table 29. Configuration/GPIO Pins (Sheet Signal Name GPIO[6:5] IO GPIO[7] Total (per channel) 3.2.11 Pin State During Reset In addition to the configuration pins listed in TST_RESET_L must always be tied high. ...

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SlowPort Clock Behavior During Reset In IXP2400 A0 silicon, when the SYS_RESET_L or the PCI_RST_L is asserted, the SP_CLK drives out the clock signal at the same frequency as the SYS_CLK, but 180 degrees out of phase with the ...

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Intel IXP2400 Network Processor 3.4 Ball Information Figure 10. IXP2400 Network Processor Ball Map (bottom left side) Bottom View D_BA[1] VSS VCC2.5 ECC[3] DQS[ VSS ECC[7] DQ[37 ...

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Figure 11. IXP2400 Network Processor Ball Map (bottom right side) Bottom View VCC3.3 TXDATA TXDATA 2 [27] [21] TXENB 3 VCC3.3 [2] TXDATA 4 [22] TXERR VCC3.3 5 [2] TXDATA TXDATA 6 [31] [23] TXSOF VCC3.3 7 ...

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IXP2400 Network Processor 3.5 Ball List Tables Table 30 defines the signal types on the ball list. ) Table 30. IXP2400 Network Processor Signal-Type Abbreviations Ball Abbreviation VCC3.3 VCC2.5 VCC1.5 VCC VSS VCCA VSSA PD OD DNC 3.5.1 Balls Listed ...

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Ball Signal Name Location D_DQ[10] C15 D_DQ[11] H16 D_DQ[12] G16 D_DQ[13] D16 D_DQ[14] D13 D_DQ[15] H17 D_DQ[16] F14 D_DQ[17] C11 D_DQ[18] D10 D_DQ[19] C8 D_DQ[2] B14 D_DQ[20] D15 D_DQ[21] D12 D_DQ[22] B11 D_DQ[23] A9 D_DQ[24] E11 D_DQ[25] A6 D_DQ[26] D7 ...

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IXP2400 Network Processor Ball Signal Name Location PCI_AD[24] AP22 PCI_AD[25] AT22 PCI_AD[26] AU22 PCI_AD[27] AL21 PCI_AD[28] AM21 PCI_AD[29] AP21 PCI_AD[3] AM28 PCI_AD[30] AR21 PCI_AD[31] AT21 PCI_AD[32] AP37 PCI_AD[33] AR37 PCI_AD[34] AT37 PCI_AD[35] AM36 PCI_AD[36] AN36 PCI_AD[37] AP36 PCI_AD[38] AT36 PCI_AD[39] ...

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Ball Signal Name Location RXDATA[26] AT11 RXDATA[27] AP14 RXDATA[28] AU12 RXDATA[29] AT15 RXDATA[3] AP2 RXDATA[30] AT14 RXDATA[31] AU14 RXDATA[4] AR7 RXDATA[5] AP4 RXDATA[6] AR3 RXDATA[7] AT4 RXDATA[8] AT5 RXDATA[9] AT6 RXENB[0] AP11 RXENB[1] AN8 RXENB[2] AM15 RXENB[3] AR9 RXEOF[0] AL1 ...

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IXP2400 Network Processor Ball Signal Name Location S0_K_L[1] C32 S0_PI[0] F21 S0_PI[1] C23 S0_PO[0] F36 S0_PO[1] A36 S0_RPE_L[0] D30 S0_RPE_L[1] C33 S0_VREF A24 S0_WPE_L[0] C34 S0_WPE_L[1] C37 S0_ZQ[0] J30 S0_ZQ[1] H29 S1_A[0] U36 S1_A[1] T35 S1_A[10] R35 S1_A[11] R36 S1_A[12] ...

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Ball Signal Name Location SYS_RESET_L AG35 SYS_RESET_OUT_L AH36 T_DIAG_CLK AH30 T_LOAD AK32 T_SYS_REFCLK AM18 TCK AG30 TDI_T_SCAN_EN AL33 TDO AG33 THERMDA J18 THERMDC J19 TMS_T_CLK AJ32 TRST_L AG31 TST_RESET_L AL32 TXADDR[0] AK2 TXADDR[1] AJ8 TXADDR[2] AK1 TXADDR[3] AL3 TXCDATA[0] AL13 ...

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IXP2400 Network Processor Ball Signal Name Location VCC AA27 VCC W27 VCC U27 VCC R27 VCC N27 VCC L27 VCC J27 VCC AK26 VCC AH26 VCC AF26 VCC AD26 VCC AB26 VCC Y26 VCC V26 VCC T26 VCC P26 VCC ...

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Ball Signal Name Location VCC L17 VCC J17 VCC AK16 VCC AH16 VCC AF16 VCC AD16 VCC AB16 VCC Y16 VCC V16 VCC T16 VCC P16 VCC M16 VCC K16 VCC AJ15 VCC AG15 VCC AE15 VCC AC15 VCC AA15 ...

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IXP2400 Network Processor Ball Signal Name Location VCC1.5 H31 VCC1.5 AD30 VCC1.5 AB30 VCC1.5 Y30 VCC1.5 V30 VCC1.5 T30 VCC1.5 P30 VCC1.5 M30 VCC1.5 K30 VCC1.5 G30 VCC1.5 E30 VCC1.5 B30 VCC1.5 H28 VCC1.5 E28 VCC1.5 B28 VCC1.5 H26 VCC1.5 ...

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Ball Signal Name Location VCC3.3 AA1 VCCA AP18 VCCA AN18 VSS AL37 VSS AH37 VSS AE37 VSS AC37 VSS AA37 VSS U37 VSS R37 VSS N37 VSS M37 VSS L37 VSS J37 VSS H37 VSS G37 VSS F37 VSS D37 ...

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IXP2400 Network Processor Ball Signal Name Location VSS AD25 VSS AB25 VSS Y25 VSS V25 VSS T25 VSS P25 VSS M25 VSS K25 VSS G25 VSS D25 VSS A25 VSS AR24 VSS AL24 VSS AJ24 VSS AG24 VSS AE24 VSS ...

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Ball Signal Name Location VSS M17 VSS K17 VSS G17 VSS D17 VSS A17 VSS AR16 VSS AL16 VSS AJ16 VSS AG16 VSS AE16 VSS AC16 VSS AA16 VSS W16 VSS U16 VSS R16 VSS N16 VSS L16 VSS J16 ...

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IXP2400 Network Processor Ball Signal Name Location VSS AG8 VSS AC8 VSS W8 VSS V8 VSS U8 VSS T8 VSS R8 VSS P8 VSS U7 VSS T7 VSS R7 VSS P7 VSS M7 VSS J7 VSS F7 VSS C7 VSS ...

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Balls Listed in Alphanumeric Order by Ball Location The following ball locations are not associated with a signal, therefore are not listed in Y37, W37, V37, AU[18:20], and A[18:20]. Table 32 shows the ball locations and signal names arranged ...

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IXP2400 Network Processor Ball Signal Name Location AB24 VCC AB25 VSS AB26 VCC AB27 VSS AB28 VCC AB29 VSS AB30 VCC1.5 AB31 S1_ZQ[1] AB32 S1_DO[0] AB33 VCC1.5 AB34 S1_DO[4] AB35 S1_DO[5] AB36 VCC1.5 AB37 S1_DO[8] AC1 TXRCOMP AC2 VSS AC3 ...

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Ball Signal Name Location AE27 VCC AE28 VSS AE29 VCC AE30 GPIO[4] AE31 VSS AE32 SP_RD_L AE33 SP_DIR_SP_A[1] AE34 VCC3.3 AE35 SP_CS_L[0] AE36 SP_AD[2] AE37 VSS AF1 TXPFA AF2 RSVD[1] AF3 TXFA[1] AF4 TXPADL[0] AF5 TXDATA[15] AF6 TXPADL[1] AF7 RXCFC ...

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IXP2400 Network Processor Ball Signal Name Location AH30 T_DIAG_CLK AH31 VSS AH32 VCC3.3 AH33 VSS AH34 VCC3.3 AH35 PLL_DIV_BYPASS AH36 SYS_RESET_OUT_L AH37 VSS AJ1 VCC3.3 AJ2 TXDATA[2] AJ3 VCC3.3 AJ4 TXDATA[3] AJ5 VCC3.3 AJ6 RSVD[0] AJ7 VCC3.3 AJ8 TXADDR[1] AJ9 ...

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Ball Signal Name Location AL33 TDI_T_SCAN_EN AL34 VCC3.3 AL35 SP_CP_SP_A[0] AL36 SP_CLK AL37 VSS AM1 TXERR[0] AM2 TXPRTY[0] AM3 TXERR[1] AM4 RXVAL[0] AM5 RXERR[0] AM6 RXVAL[1] AM7 TXCFC AM8 RXPADL[0] AM9 RSVD[3] AM10 RXADDR[3] AM11 TXCDATA[2] AM12 TXCSOF AM13 TXCDATA[1] ...

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IXP2400 Network Processor Ball Signal Name Location AP36 PCI_AD[37] AP37 PCI_AD[32] AR1 RXEOF[1] AR2 VSS AR3 RXDATA[6] AR4 VSS AR5 RXDATA[13] AR6 VSS AR7 RXDATA[4] AR8 VSS AR9 RXENB[3] AR10 VSS AR11 RXDATA[23] AR12 VSS AR13 RXDATA[20] AR14 VSS AR15 ...

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Ball Signal Name Location B5 D_ECC[2] B6 VCC2.5 B7 D_A[3] B8 D_A[11] B9 VSS B10 D_A[9] B11 D_DQ[22] B12 VCC2.5 B13 D_DQS[0] B14 D_DQ[2] B15 VSS B16 D_CKE[0] B17 D_DQ[3] B18 VCC2.5 B19 VSS B20 VCC1.5 B21 S0_DI[10] B22 VCC1.5 ...

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IXP2400 Network Processor Ball Signal Name Location E8 D_DQS[3] E9 VSS E10 D_DQ[28] E11 D_DQ[24] E12 VCC2.5 E13 D_DM[2] E14 D_DQS[1] E15 VSS E16 D_DQ[9] E17 D_DQ[6] E18 VCC2.5 E19 S0_DI[13] E20 VCC1.5 E21 S0_CIN[0] E22 VCC1.5 E23 S0_DI[2] E24 ...

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Ball Signal Name Location H11 D_ECC[1] H12 VCC2.5 H13 D_DQ[31] H14 D_DQ[27] H15 VSS H16 D_DQ[11] H17 D_DQ[15] H18 VCC2.5 H19 S0_DI[14] H20 VCC1.5 H21 VSS H22 VCC1.5 H23 S0_DI[0] H24 VCC1.5 H25 S0_A[2] H26 VCC1.5 H27 S0_BWE_L[1] H28 VCC1.5 ...

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IXP2400 Network Processor Ball Signal Name Location L14 VSS L15 VCC L16 VSS L17 VCC L18 VSS L19 VCC L20 VSS L21 VCC L22 VSS L23 VCC L24 VSS L25 VCC L26 VSS L27 VCC L28 VSS L29 VCC L30 ...

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Ball Signal Name Location P17 VSS P18 VCC P19 VSS P20 VCC P21 VSS P22 VCC P23 VSS P24 VCC P25 VSS P26 VCC P27 VSS P28 VCC P29 VSS P30 VCC1.5 P31 S1_A[16] P32 S1_A[17] P33 VCC1.5 P34 S1_A[14] ...

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IXP2400 Network Processor Ball Signal Name Location U20 VSS U21 VCC U22 VSS U23 VCC U24 VSS U25 VCC U26 VSS U27 VCC U28 VSS U29 VCC U30 S1_BWE_L[0] U31 VSS U32 S1_K_L[0] U33 S1_A[4] U34 VSS U35 S1_C_L[1] U36 ...

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Ball Signal Name Location Y28 VCC Y29 VSS Y30 VCC1.5 Y31 S1_DO[9] Y32 S1_DO[12] Y33 VCC1.5 Y34 S1_DO[13] Y35 S1_PO[1] Y36 VCC1.5 Datasheet IXP2400 Network Processor 97 ...

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Intel IXP2400 Network Processor 4.0 Electrical Specifications This chapter specifies the following electrical behavior of the IXP2400: • Absolute maximum ratings • DC values and AC timing specifications for the following: — PCI I/O Unit — QDR — DDR ...

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Table 34. Functional Operating Voltage Range Voltage (V) Supply 400 MHz Name (B Stepping) VCC1.3 1.1 VCCA1.3 1.1 VCC2.5 2.5 VCC1.5 1.50 VCC3.3 3.3 1. For A-stepping (400-MHz) IXP2400, VCC1.3 and VCCA1.3 is 1.3V. Table 35. Power Totals for B ...

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Intel IXP2400 Network Processor Table 37. Maximum Power Consumption by Power Supply Supply Name 400 MHz (1.3V) VCC1.3 8.92 VCCA1.3 3 VCC1.5 2.67 3 VCC2.5 3.15 VCC3.3 2.97 Totals 17.71 1. Values presented include core and I/O. 2. 400-MHz ...

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Use only 32-bit and/or 33-MHz PCI adequate for the application. Power consumption in such cases is lower than PCI 64-bit/66-MHz. 4.2 AC/DC Specifications 4.2.1 Clock Timing Specifications Figure 13. SYS_CLK Timing Table 38. SYS_CLK DC Specification ...

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Intel IXP2400 Network Processor • Absolute maximum ratings • DC specifications • AC timing specifications 4.2.2.1 PCI Absolute Maximum Ratings Table 40. Absolute Maximum PCI Ratings Parameter Maximum voltage applied to signal pins Supply voltage (I/O), VCC3.3 The power ...

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Table 43. Overshoot/Undershoot Specifications Pin Type Input Output Bidirectional 4.2.2.4 PCI AC Specifications The AC specifications consist of input requirements and output responses. The input requirements consist of setup and hold times, pulse widths, and high and low times. Output ...

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Intel IXP2400 Network Processor Table 45. 33-MHz PCI Clock Signal AC Parameters Symbol T cyc T high T low — 1. 0.3 VCC3.3 to 0.6 VCC3.3. Figure 15. PCI Bus Signals PCI_CLK Outputs Inputs Note 0.4 VCC3.3 ...

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Bused signals are AD, CBE_L, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, DEVSEL_L, STOP_L 4. These parameters are at variance with those in the PCI Local Bus Specification, Revision 2.2 . Table 47. 66-MHz PCI Signal Timing Symbol T val ...

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Intel IXP2400 Network Processor Figure 16. QDR Load Circuit Table 49. QDR and QDRII Signal Timing Parameters Symbol Parameter Tcycle Clock cycle time Tvalmin Tval clock to data output valid (K/K#) Tvalmax Tval_a_ Clock to R/W min control output ...

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Figure 17. QDRII Timing Reference val_a_max t val_a_min A/R#/W# t val_max t val_min 4.2.4 DDR SDRAM Table 50 lists the DDR SDRAM DC parameters. Table 50. DDR SDRAM DC ...

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Intel IXP2400 Network Processor Table 50. DDR SDRAM DC Parameters for 100/150 MHz (Continued) Symbol VIL (AC) DDR input low voltage, AC VIH (AC) DDR input high voltage DDR input/output pin capacitance IO Table 51. DDR SDRAM ...

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Table 51. DDR SDRAM AC Parameters for 100/150 MHz (Continued) Symbol T D_DQS Write Postamble Duration WPST D_CK Rising Edge Output Access Time, Where a Write Command is T DQSS Referenced, to the First D_DQS Rising Edge D_CK Rising Edge ...

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Intel IXP2400 Network Processor Figure 19. Data and Error Correction Valid Before and After Data Strobe (Write Operation) D_DQS D_DQ, D_ECC Figure 20. Write Preamble Duration D_DQS Figure 21. Write Postamble Duration D_DQS Figure 22. Command Signals Valid Before ...

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Figure 23. Clock Enable Valid Before and After Clock Rising Edge D_CK_L[2:0] D_DQS D_CKE[1:0] Figure 24. Chip Select Valid Before and After Clock Rising Edge D_DQS D_CS[1:0] D_DM[8:0] Figure 25. Clock Cycle Time D_CK_L[2:0] D_CK[2:0] Figure 26. Skew Between Any ...

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Intel IXP2400 Network Processor Figure 27. Clock High Time D_CK_L[2:0] D_CK[2:0] Figure 28. Clock Low Time D_CK_L[2:0] D_CK[2:0] Figure 29. Data Strobe Falling Edge Output Access Time to Clock Rising Edge D_CK_L[2:0] D_CK[2:0] D_DQS Figure 30. Data Strobe Falling ...

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Figure 31. Clock Rising Edge Output Access Time to the First Data Strobe Rising Edge D_CK_L[2:0] D_CK[2:0] D_A[12:0], D_BA, D_RAS_L, D_CAS_L, D_WE_L D_DQS Figure 32. Clock Rising Edge Output Access Time to the Data Strobe Preamble Falling Edge D_CK_L[2:0] D_CK[2:0] ...

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Intel IXP2400 Network Processor Figure 34. Input Clock Falling Edge Setup Time to the First Data Strobe Rising Edge D_DQS D_RCVENIN_L Figure 35. Input Clock Rising Edge Hold Time from the First Data Strobe Rising Edge D_DQS D_RCVENIN_L Figure ...

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DC Parameters Table 52 lists applicable DC thresholds for the MSF. ) Table 52. MSF (LVTTL) DC Thresholds Symbol Vih Vil Voh Vol I Leak Cload Table 53. MSF Overshoot/Undershoot Specifications Pin Type Input Output 4.2.5.2 Media Clocks Figure ...

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Intel IXP2400 Network Processor Table 55. Media Clock AC Specifications Symbol T CLK cycle time cyc T CLK high time high T CLK low time low — CLK slew rate 1. 0.3 VCC3.3 to 0.6 VCC3.3 2. Includes RXCLK01, ...

Page 117

Figure 38. Receive UTOPIA/POS/CSIX RXADDR, RXENB RXCLK01 RXCLK23 RXEOF, RXPADL, RXVAL, RXDATA, RXPRTY, RXSOF, RXDERR, RXPFA, RXFA Figure 39. Transmit UTOPIA/POS/CSIX TXDATA, TXPRTY, TXSOF, TXADDR, TXENB TXEOF, TXPADL, TXERR TXCLK01 TXCLK23 TXPFA, TXSFA, TXFA 4.2.6 CBus Table 57 lists applicable ...

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Intel IXP2400 Network Processor 4.2.7 SlowPort, GPIO, and Serial I/O Buffer Table 58 lists the AC and DC parameters for the SlowPort and GPIO. The GPIO can be used with appropriate software in I for the DC and AC ...

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Figure 40. Mode 0 Single Write Transfer for Self-Timing Device — SlowPort t t CO_fall CO_rise 0 2 P_CLK SP_CLK t co SP_ALE_L SP_CS_L [1:0] SP_WR_L SP_RD_L SP_ACK_L t co SP_A[1:0] SP_AD[7:0] 9:2 17:10 Table 59. SlowPort Write Timing tco ...

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Intel IXP2400 Network Processor Figure 41. Mode 0 Single Read Transfer for Self-Timing Device — SlowPort t t CO_rise CO_fall 0 2 P_CLK SP_CLK SP_ALE_L SP_CS_L[1:0] SP_WR_L SP_RD_L SP_A[1:0] SP_AD[7:0] 9:2 17:10 SP_ACK_L t co Table 60. SlowPort Read ...

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The pulse width depends on the pulse-width parameter set in the SP_RTC1 and SP_RTC2 registers and the clock di- visor as well. The minimum for one clock cycle at 50 MHz. 4.2.8 JTAG 4.2.8.1 JTAG DC ...

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Intel IXP2400 Network Processor Figure 43. Boundary Scan Tristate Timing tck tdo Data Out Figure 44. Boundary Scan Reset Timing ntrst tms Table 62. JTAG AC Specifications Symbol Tbscl TCK low period Tbsch TCK high period Tbsis TDI, TMS ...

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Table 62. JTAG AC Specifications (Continued) Symbol Tbsdz Data output disable time Tbsr Reset period Tbsrs TMS setup to ntrst Tbsrh TMS hold from ntrst 1. Assumes load on TDO. Output timing derates at 0.072 ns/pF of ...

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Intel IXP2400 Network Processor 5.0 Mechanical Specifications 5.1 Package Dimensions The IXP2400 is contained in a 1356 package, as shown in described in Table 63. Figure 45. IXP2400 Network Processor General Mechanical Drawing E F1 TOP VIEW Table 63. ...

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Table 63. IXP2400 Network Processor Package Dimensions (Continued) Symbol NOTE: Measurements in millimeters. Table 64. IXP2400 Network Processor Die Size X 17.20 NOTE: Measurements in millimeters. Datasheet 1356 BGA Minimum Maximum 37.45 37.55 ...

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Intel IXP2400 Network Processor This page is intentionally left blank. 126 Datasheet ...

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